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[24.205.208.113]) by smtp.gmail.com with ESMTPSA id u3-20020a056808114300b002d51f9b3263sm5328725oiu.28.2022.03.06.07.37.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Mar 2022 07:37:48 -0800 (PST) Subject: Re: [PATCH V1 RESEND 2/4] Documentation: devicetree: bindings: add binding for PCIe endpoint bus To: Lizhi Hou , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org Cc: yilun.xu@intel.com, maxz@xilinx.com, sonal.santan@xilinx.com, yliu@xilinx.com, michal.simek@xilinx.com, stefanos@xilinx.com, mdf@kernel.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org, Max Zhen References: <20220305052304.726050-1-lizhi.hou@xilinx.com> <20220305052304.726050-3-lizhi.hou@xilinx.com> From: Tom Rix Message-ID: Date: Sun, 6 Mar 2022 07:37:46 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20220305052304.726050-3-lizhi.hou@xilinx.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Lizhi, Sorry for the delay, I am fighting with checking this with 'make dt_binding_check' There is a recent failure in linux-next around display/mediatek,* between next-20220301 and next-20220302 that I am bisecting. There are a couple of checkpatch --strict warnings for this set, the obvious one is adding to the MAINTAINERS for new files. Tom On 3/4/22 9:23 PM, Lizhi Hou wrote: > Create device tree binding document for PCIe endpoint bus. > > Signed-off-by: Sonal Santan > Signed-off-by: Max Zhen > Signed-off-by: Lizhi Hou > --- > .../devicetree/bindings/bus/pci-ep-bus.yaml | 72 +++++++++++++++++++ > 1 file changed, 72 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/pci-ep-bus.yaml > > diff --git a/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml > new file mode 100644 > index 000000000000..0ca96298db6f > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml > @@ -0,0 +1,72 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/pci-ep-bus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PCIe Endpoint Bus binding > + > +description: | > + PCIe device may use flattened device tree to describe apertures in its > + PCIe BARs. The Bus PCIe endpoint node is created and attached under the > + device tree root node for this kind of device. Then the flatten device > + tree overlay for this device is attached under the endpoint node. > + > + The aperture address which is under the endpoint node consists of BAR > + index and offset. It uses the following encoding: > + > + 0xIooooooo 0xoooooooo > + > + Where: > + > + I = BAR index > + oooooo oooooooo = BAR offset > + > + The endpoint is compatible with 'simple-bus' and contains 'ranges' > + property for translating aperture address to CPU address. > + > +allOf: > + - $ref: /schemas/simple-bus.yaml# > + > +maintainers: > + - Lizhi Hou > + > +properties: > + compatible: > + contains: > + const: pci-ep-bus > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: hardware apertures belong to this device. > + type: object > + > +required: > + - compatible > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + pci-ep-bus@e0000000 { > + compatible = "pci-ep-bus", "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000 > + 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>; > + }; > + };