From: Kishon Vijay Abraham I <kishon@ti.com>
To: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq
Date: Thu, 28 Dec 2017 13:36:28 +0530 [thread overview]
Message-ID: <e8a50bf0-edab-db41-0c80-13a1509e289c@ti.com> (raw)
In-Reply-To: <20171227222909.GA14106@axis.com>
Hi Niklas,
On Thursday 28 December 2017 03:59 AM, Niklas Cassel wrote:
> On Tue, Dec 26, 2017 at 06:20:54PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Niklas,
>
> Hello Kishon
>
>>
>> On Wednesday 20 December 2017 04:59 AM, Niklas Cassel wrote:
>>> Add a generic function for raising MSI irqs that can be used by all
>>> DWC based controllers.
>>>
>>> Note that certain controllers, like DRA7xx, have a special convenience
>>> register for raising MSI irqs that doesn't require you to explicitly map
>>> the MSI address. Therefore, it is likely that certain drivers will
>>> not use this generic function, even if they can.
>>>
>>> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
>>> ---
>>> drivers/pci/dwc/pcie-designware-ep.c | 35 +++++++++++++++++++++++++++++++++++
>>> drivers/pci/dwc/pcie-designware.h | 9 +++++++++
>>> 2 files changed, 44 insertions(+)
>>>
>>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
>>> index 700ed2f4becf..c5aa1cac5041 100644
>>> --- a/drivers/pci/dwc/pcie-designware-ep.c
>>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>>> @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops = {
>>> .stop = dw_pcie_ep_stop,
>>> };
>>>
>>> +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
>>> + u8 interrupt_num)
>>> +{
>>> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>> + struct pci_epc *epc = ep->epc;
>>> + u16 msg_ctrl, msg_data;
>>> + u32 msg_addr_lower, msg_addr_upper;
>>> + u64 msg_addr;
>>> + bool has_upper;
>>> + int ret;
>>> +
>>> + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
>>> + msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
>>> + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
>>> + msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
>>> + if (has_upper) {
>>> + msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
>>> + msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
>>> + } else {
>>> + msg_addr_upper = 0;
>>> + msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
>>> + }
>>> + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
>>> + ret = dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,
>>> + epc->mem->page_size);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
>>
>> Shouldn't this be msg_data + (interrupt_num - 1)?
>
> I'm not quite sure about this, but if there is a pending irq,
> not yet processed by the RC, the msg_data we read out in this
> function should have a bit set, matching the pending irq.
IIUC, the msg_data that we read here should not depend on the pending irq on
the RC side. msg_data should have the starting MSI vector number assigned by RC
for that EP device. (msg.data = pos; in dw_msi_setup_msg() also seem to suggest
the same).
>
> If that irq is the same as the irq we are trying to raise,
> doing an addition will produce a bogus vector number,
> but a bitwise or should work.
if msg_data has the starting MSI vector, doing an addition should get to the
correct MSI vector.
>
> For that reason, I think that doing bitwise or seems safer.
> However, other than this case, I don't see why it should
> matter if we do an addition or a bitwise or.
>
> Are you having some problem with the code?
> It seems to be working fine on ARTPEC-6:
>
> # ./pcitest -m 1
> MSI1: OKAY
> # ./pcitest -m 2
> MSI2: OKAY
> # ./pcitest -m 3
> MSI3: OKAY
> # ./pcitest -m 4
> MSI4: OKAY
> # ./pcitest -m 5
> MSI5: OKAY
> # ./pcitest -m 6
> MSI6: OKAY
> # ./pcitest -m 7
> MSI7: OKAY
> # ./pcitest -m 8
> MSI8: OKAY
> # ./pcitest -m 9
> MSI9: OKAY
> # cat /proc/interrupts | grep -i msi
> 82: 9 0 GIC-0 180 Level artpec6-pcie-msi
> 188: 1 0 PCI-MSI 16 Edge pci-endpoint-test
> 189: 1 0 PCI-MSI 17 Edge pci-endpoint-test
> 190: 1 0 PCI-MSI 18 Edge pci-endpoint-test
> 191: 1 0 PCI-MSI 19 Edge pci-endpoint-test
> 192: 1 0 PCI-MSI 20 Edge pci-endpoint-test
> 193: 1 0 PCI-MSI 21 Edge pci-endpoint-test
> 194: 1 0 PCI-MSI 22 Edge pci-endpoint-test
> 195: 1 0 PCI-MSI 23 Edge pci-endpoint-test
> 196: 1 0 PCI-MSI 24 Edge pci-endpoint-test
> 197: 0 0 PCI-MSI 25 Edge pci-endpoint-test
> 198: 0 0 PCI-MSI 26 Edge pci-endpoint-test
> 199: 0 0 PCI-MSI 27 Edge pci-endpoint-test
> 200: 0 0 PCI-MSI 28 Edge pci-endpoint-test
> 201: 0 0 PCI-MSI 29 Edge pci-endpoint-test
> 202: 0 0 PCI-MSI 30 Edge pci-endpoint-test
> 203: 0 0 PCI-MSI 31 Edge pci-endpoint-test
>
> From EP:
> irq: 1 read msg_data: 0x10 writing: 0x10
> irq: 2 read msg_data: 0x10 writing: 0x11
> irq: 3 read msg_data: 0x10 writing: 0x12
> irq: 4 read msg_data: 0x10 writing: 0x13
> irq: 5 read msg_data: 0x10 writing: 0x14
> irq: 6 read msg_data: 0x10 writing: 0x15
> irq: 7 read msg_data: 0x10 writing: 0x16
> irq: 8 read msg_data: 0x10 writing: 0x17
> irq: 9 read msg_data: 0x10 writing: 0x18
since your msg_data is 0x10, you are not facing the issue. What if it's 0x1? In
my case If I have Gustavo's patch series applied, msg_data has a value of 0x1
and I don't get certain MSI interrupts.
Thanks
Kishon
next prev parent reply other threads:[~2017-12-28 8:06 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-19 23:29 [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 01/18] PCI: dwc: Use the DMA-API to get the MSI address Niklas Cassel
2017-12-20 19:10 ` Joao Pinto
2017-12-21 16:43 ` Jingoo Han
2020-09-23 23:18 ` Rob Herring
2017-12-19 23:29 ` [PATCH v6 02/18] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-12-20 19:17 ` Joao Pinto
2017-12-21 16:44 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 03/18] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-12-20 19:18 ` Joao Pinto
2017-12-21 16:45 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 04/18] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-12-20 19:30 ` Joao Pinto
2017-12-21 16:46 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 05/18] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-12-20 19:32 ` Joao Pinto
2017-12-21 16:47 ` Jingoo Han
2017-12-26 12:50 ` Kishon Vijay Abraham I
2017-12-27 22:29 ` Niklas Cassel
2017-12-28 8:06 ` Kishon Vijay Abraham I [this message]
2017-12-28 14:39 ` Kishon Vijay Abraham I
2017-12-28 22:43 ` Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 07/18] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 08/18] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 09/18] PCI: dwc: dra7xx: Help compiler to remove unused code Niklas Cassel
2017-12-20 5:58 ` Kishon Vijay Abraham I
2017-12-19 23:29 ` [PATCH v6 10/18] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 11/18] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 12/18] PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 13/18] bindings: PCI: artpec: Add support for endpoint mode Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 14/18] PCI: dwc: artpec6: " Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 15/18] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-12-20 5:52 ` Kishon Vijay Abraham I
2017-12-19 23:29 ` [PATCH v6 16/18] PCI: dwc: artpec6: Deassert the core before waiting for PHY Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 17/18] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 18/18] PCI: dwc: artpec6: " Niklas Cassel
2017-12-20 17:34 ` [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Lorenzo Pieralisi
2017-12-20 19:47 ` Joao Pinto
2017-12-20 23:22 ` Niklas Cassel
2017-12-21 9:23 ` Joao Pinto
2017-12-21 10:02 ` Lorenzo Pieralisi
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