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Subject: Re: [PATCH V4 1/2] PCI: dwc: Add API support to de-initialize host
To:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC:     <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
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From:   Vidya Sagar <vidyas@nvidia.com>
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Date:   Tue, 18 Jun 2019 16:21:17 +0530
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On 6/18/2019 3:06 PM, Lorenzo Pieralisi wrote:
> On Tue, Jun 18, 2019 at 10:19:14AM +0530, Vidya Sagar wrote:
>=20
> [...]
>=20
>> Sorry for pinging again. Please let me know if these patches need to
>> be sent again.
>=20
> No problem. We can merge the code as-is even though I have a couple
> of questions.
>=20
> 1) What about dbi2 interfaces (what an horrible name it is :() ? It
>     is true that it is probably best to export just what we need.
I see that dbi2 API (that too only write) is used by pci-keystone and it
is described as a bool driver currently. I'm not sure if it will ever be
made as a modular driver.

> 2) It is not related to this patch but I fail to see the reasoning
>     behind the __ in __dw_pci_read_dbi(), there is no no-underscore
>     equivalent so its definition is somewhat questionable, maybe
>     we should clean-it up (for dbi2 alike).
Separate no-underscore versions are present in pcie-designware.h for each w=
idth
(i.e. l/w/b) as inline and are calling __ versions passing size as argument=
.

>=20
> Lorenzo
>=20
>> Thanks,
>> Vidya Sagar
>>
>>>
>>>>
>>>>>>
>>>>>>>
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Lorenzo
>>>>>>>>
>>>>>>>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/=
drivers/pci/controller/dwc/pcie-designware-host.c
>>>>>>>>> index 77db32529319..d069e4290180 100644
>>>>>>>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
>>>>>>>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
>>>>>>>>> @@ -496,6 +496,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>>>>>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret;
>>>>>>>>>  =C2=A0 }
>>>>>>>>> +void dw_pcie_host_deinit(struct pcie_port *pp)
>>>>>>>>> +{
>>>>>>>>> +=C2=A0=C2=A0=C2=A0 pci_stop_root_bus(pp->root_bus);
>>>>>>>>> +=C2=A0=C2=A0=C2=A0 pci_remove_root_bus(pp->root_bus);
>>>>>>>>> +=C2=A0=C2=A0=C2=A0 if (pci_msi_enabled() && !pp->ops->msi_host_i=
nit)
>>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dw_pcie_free_msi(pp);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>>  =C2=A0 static int dw_pcie_access_other_conf(struct pcie_port *pp=
, struct pci_bus *bus,
>>>>>>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u32 d=
evfn, int where, int size, u32 *val,
>>>>>>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool =
write)
>>>>>>>>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drive=
rs/pci/controller/dwc/pcie-designware.h
>>>>>>>>> index deab426affd3..4f48ec78c7b9 100644
>>>>>>>>> --- a/drivers/pci/controller/dwc/pcie-designware.h
>>>>>>>>> +++ b/drivers/pci/controller/dwc/pcie-designware.h
>>>>>>>>> @@ -348,6 +348,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
>>>>>>>>>  =C2=A0 void dw_pcie_free_msi(struct pcie_port *pp);
>>>>>>>>>  =C2=A0 void dw_pcie_setup_rc(struct pcie_port *pp);
>>>>>>>>>  =C2=A0 int dw_pcie_host_init(struct pcie_port *pp);
>>>>>>>>> +void dw_pcie_host_deinit(struct pcie_port *pp);
>>>>>>>>>  =C2=A0 int dw_pcie_allocate_domains(struct pcie_port *pp);
>>>>>>>>>  =C2=A0 #else
>>>>>>>>>  =C2=A0 static inline irqreturn_t dw_handle_msi_irq(struct pcie_p=
ort *pp)
>>>>>>>>> @@ -372,6 +373,10 @@ static inline int dw_pcie_host_init(struct p=
cie_port *pp)
>>>>>>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0;
>>>>>>>>>  =C2=A0 }
>>>>>>>>> +static inline void dw_pcie_host_deinit(struct pcie_port *pp)
>>>>>>>>> +{
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>>  =C2=A0 static inline int dw_pcie_allocate_domains(struct pcie_po=
rt *pp)
>>>>>>>>>  =C2=A0 {
>>>>>>>>>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0;
>>>>>>>>> --=20
>>>>>>>>> 2.17.1
>>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>