From: Dilip Kota <eswara.kota@linux.intel.com>
To: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"andrew.murray@arm.com" <andrew.murray@arm.com>,
"helgaas@kernel.org" <helgaas@kernel.org>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"robh@kernel.org" <robh@kernel.org>,
"martin.blumenstingl@googlemail.com"
<martin.blumenstingl@googlemail.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"andriy.shevchenko@intel.com" <andriy.shevchenko@intel.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"cheol.yong.kim@intel.com" <cheol.yong.kim@intel.com>,
"chuanhua.lei@linux.intel.com" <chuanhua.lei@linux.intel.com>,
"qi-ming.wu@intel.com" <qi-ming.wu@intel.com>
Subject: Re: [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver
Date: Thu, 14 Nov 2019 11:51:58 +0800 [thread overview]
Message-ID: <ec2e7ef1-b549-f8f7-d5f3-908c534bbd4f@linux.intel.com> (raw)
In-Reply-To: <CH2PR12MB40074C910983FF97DDCF8478DA760@CH2PR12MB4007.namprd12.prod.outlook.com>
On 11/13/2019 5:59 PM, Gustavo Pimentel wrote:
> On Wed, Nov 13, 2019 at 7:21:21, Dilip Kota <eswara.kota@linux.intel.com>
> wrote:
>
[...]
> +static struct platform_driver intel_pcie_driver = {
> + .probe = intel_pcie_probe,
> + .remove = intel_pcie_remove,
> + .driver = {
> + .name = "intel-gw-pcie",
> + .of_match_table = of_intel_pcie_match,
> + .pm = &intel_pcie_pm_ops,
> + },
> +};
> +builtin_platform_driver(intel_pcie_driver);
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 29d6e93fd15e..548e22e07a52 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -673,6 +673,7 @@
> #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
> #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
> #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
> +#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
> #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
> #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
> #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
> --
> 2.11.0
>
> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Thanks for reviewing the patch.
Regards,
Dilip
>
>
next prev parent reply other threads:[~2019-11-14 3:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-13 7:21 [PATCH v6 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-11-13 7:21 ` [PATCH v6 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-11-13 7:21 ` [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-11-13 9:59 ` Gustavo Pimentel
2019-11-14 3:51 ` Dilip Kota [this message]
2019-11-13 11:00 ` Andy Shevchenko
2019-11-14 3:52 ` Dilip Kota
2019-11-13 7:21 ` [PATCH v6 3/3] PCI: artpec6: Configure FTS with dwc helper function Dilip Kota
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