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[219.120.4.122]) by smtp.gmail.com with ESMTPSA id h23sm28875432pfn.68.2019.03.27.20.19.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Mar 2019 20:19:44 -0700 (PDT) Subject: Re: [PATCH V4 6/6] PCI: rcar: Fix 64bit MSI message address handling To: Geert Uytterhoeven , Simon Horman Cc: linux-pci , Marek Vasut , Geert Uytterhoeven , Phil Edworthy , Wolfram Sang , Linux-Renesas References: <20190325114101.10198-1-marek.vasut@gmail.com> <20190325114101.10198-6-marek.vasut@gmail.com> <20190327113023.zhnx5v5spcx7uoqj@verge.net.au> From: Marek Vasut Openpgp: preference=signencrypt Message-ID: Date: Thu, 28 Mar 2019 04:03:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 3/27/19 1:22 PM, Geert Uytterhoeven wrote: > On Wed, Mar 27, 2019 at 12:30 PM Simon Horman wrote: >> On Mon, Mar 25, 2019 at 12:41:01PM +0100, marek.vasut@gmail.com wrote: >>> From: Marek Vasut >>> The MSI message address in the RC address space can be 64 bit. The >>> R-Car PCIe RC supports such a 64bit MSI message address as well. >>> The code currently uses virt_to_phys(__get_free_pages()) to obtain >>> a reserved page for the MSI message address, and the return value >>> of which can be a 64 bit physical address on 64 bit system. >>> >>> However, the driver only programs PCIEMSIALR register with the bottom >>> 32 bits of the virt_to_phys(__get_free_pages()) return value and does >>> not program the top 32 bits into PCIEMSIAUR, but rather programs the >>> PCIEMSIAUR register with 0x0. This worked fine on older 32 bit R-Car >>> SoCs, however may fail on new 64 bit R-Car SoCs. >>> >>> Since from a PCIe controller perspective, an inbound MSI is a memory >>> write to a special address (in case of this controller, defined by >>> the value in PCIEMSIAUR:PCIEMSIALR), which triggers an interrupt, but >>> never hits the DRAM _and_ because allocation of an MSI by a PCIe card >>> driver obtains the MSI message address by reading PCIEMSIAUR:PCIEMSIALR >>> in rcar_msi_setup_irqs(), incorrectly programmed PCIEMSIAUR cannot >>> cause memory corruption or other issues. >>> >>> There is however the possibility that if virt_to_phys(__get_free_pages()) >>> returned address above the 32bit boundary _and_ PCIEMSIAUR was programmed >>> to 0x0 _and_ if the system had physical RAM at the address matching the >>> value of PCIEMSIALR, a PCIe card driver could allocate a buffer with a >>> physical address matching the value of PCIEMSIALR and a remote write to >>> such a buffer by a PCIe card would trigger a spurious MSI. >>> >>> Signed-off-by: Marek Vasut >>> Cc: Geert Uytterhoeven >>> Cc: Phil Edworthy >>> Cc: Simon Horman >>> Cc: Wolfram Sang >>> Cc: linux-renesas-soc@vger.kernel.org >>> To: linux-pci@vger.kernel.org >>> Reviewed-by: Geert Uytterhoeven >> >> Does this warrant a Fixes tag? > > (digging in old sent email) > Fixes: 290c1fb358605402 ("PCI: rcar: Add MSI support for PCIe") But does it really fix that commit, given that on Gen2 and earlier, it was not broken as those were 32bit platforms ? -- Best regards, Marek Vasut