From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C053C10F0E for ; Mon, 15 Apr 2019 14:56:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DA4CE21900 for ; Mon, 15 Apr 2019 14:56:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="OMa781oU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727622AbfDOO4K (ORCPT ); Mon, 15 Apr 2019 10:56:10 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2463 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727304AbfDOO4J (ORCPT ); Mon, 15 Apr 2019 10:56:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 15 Apr 2019 07:55:48 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 15 Apr 2019 07:56:07 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 15 Apr 2019 07:56:07 -0700 Received: from [10.24.70.150] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 15 Apr 2019 14:56:03 +0000 Subject: Re: [PATCH 06/30] PCI: tegra: Program UPHY electrical settings for Tegra210 To: Thierry Reding CC: , , , , , , , , References: <20190411170355.6882-1-mmaddireddy@nvidia.com> <20190411170355.6882-7-mmaddireddy@nvidia.com> <20190415112922.GG29254@ulmo> X-Nvconfidentiality: public From: Manikanta Maddireddy Message-ID: Date: Mon, 15 Apr 2019 20:25:48 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190415112922.GG29254@ulmo> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555340148; bh=tGZU2OCfp6oOW8ewCbBLrBN00Rn34ieezVLAskAShYo=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type: Content-Transfer-Encoding:Content-Language; b=OMa781oUp/gJR47m30YAoJaaYvoCMoD78rsvd247nqOZAmPWvqHSOem1z5sQSLh9p n0aMQs5dvcc3CM5WghR9JBDaROuVpTTEMsG8dS0hsuHfvTBL+nRnWxEvDvsGxD0A4y XxqbLl/PyK1AZygc/mNfDlRVbcRgRdDbY37dvOha5JLZTBmlMektIIMbLkFnOQXb9M YcaF5VHnf89BONPtBG6TuyQHaIAShp5r9fY9/Kc8hnofFQOzO+qi7lfQ3yVO31sMDC BtoEoZbie5O4c00yrBVJHOB0tpyg+Uq3d8OCzEUb/vSIwiysabxozLA7Oz/zvf1TK8 RpuIITXJzzJ5Q== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 15-Apr-19 4:59 PM, Thierry Reding wrote: > On Thu, Apr 11, 2019 at 10:33:31PM +0530, Manikanta Maddireddy wrote: >> UPHY electrical programming guidelines are documented in Tegra210 TRM. >> Program these electrical settings for proper eye diagram in Gen1 and Gen2 >> link speeds. >> >> Signed-off-by: Manikanta Maddireddy >> --- >> drivers/pci/controller/pci-tegra.c | 100 +++++++++++++++++++++++++++++ >> 1 file changed, 100 insertions(+) >> >> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c >> index 9ff1a0e2797f..a377245d254d 100644 >> --- a/drivers/pci/controller/pci-tegra.c >> +++ b/drivers/pci/controller/pci-tegra.c >> @@ -177,6 +177,32 @@ >> >> #define AFI_PEXBIAS_CTRL_0 0x168 >> >> +#define RP_ECTL_2_R1 0x00000e84 >> +#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff >> + >> +#define RP_ECTL_4_R1 0x00000e8c >> +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16) >> +#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16 >> + >> +#define RP_ECTL_5_R1 0x00000e90 >> +#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff >> + >> +#define RP_ECTL_6_R1 0x00000e94 >> +#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff >> + >> +#define RP_ECTL_2_R2 0x00000ea4 >> +#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff >> + >> +#define RP_ECTL_4_R2 0x00000eac >> +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16) >> +#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16 >> + >> +#define RP_ECTL_5_R2 0x00000eb0 >> +#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff >> + >> +#define RP_ECTL_6_R2 0x00000eb4 >> +#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff >> + >> #define RP_VEND_XP 0x00000f00 >> #define RP_VEND_XP_DL_UP (1 << 30) >> >> @@ -265,6 +291,19 @@ struct tegra_pcie_soc { >> bool has_gen2; >> bool force_pca_enable; >> bool program_uphy; >> + struct { >> + struct { >> + u32 rp_ectl_2_r1; >> + u32 rp_ectl_4_r1; >> + u32 rp_ectl_5_r1; >> + u32 rp_ectl_6_r1; >> + u32 rp_ectl_2_r2; >> + u32 rp_ectl_4_r2; >> + u32 rp_ectl_5_r2; >> + u32 rp_ectl_6_r2; >> + } regs; >> + bool enable; >> + } ectl; >> }; >> >> static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) >> @@ -491,6 +530,52 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) >> writel(value, port->base + RP_VEND_CTL1); >> } >> >> +static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) >> +{ >> + const struct tegra_pcie_soc *soc = port->pcie->soc; >> + u32 val; > u32 value for consistency. I will take care of it in V2 > >> + >> + val = readl(port->base + RP_ECTL_2_R1); >> + val &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_2_r1; >> + writel(val, port->base + RP_ECTL_2_R1); >> + >> + val = readl(port->base + RP_ECTL_4_R1); >> + val &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_4_r1 << RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT; >> + writel(val, port->base + RP_ECTL_4_R1); >> + >> + val = readl(port->base + RP_ECTL_5_R1); >> + val &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_5_r1; >> + writel(val, port->base + RP_ECTL_5_R1); >> + >> + val = readl(port->base + RP_ECTL_6_R1); >> + val &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_6_r1; >> + writel(val, port->base + RP_ECTL_6_R1); >> + >> + val = readl(port->base + RP_ECTL_2_R2); >> + val &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_2_r2; >> + writel(val, port->base + RP_ECTL_2_R2); >> + >> + val = readl(port->base + RP_ECTL_4_R2); >> + val &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_4_r2 << RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT; >> + writel(val, port->base + RP_ECTL_4_R2); >> + >> + val = readl(port->base + RP_ECTL_5_R2); >> + val &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_5_r2; >> + writel(val, port->base + RP_ECTL_5_R2); >> + >> + val = readl(port->base + RP_ECTL_6_R2); >> + val &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK; >> + val |= soc->ectl.regs.rp_ectl_6_r2; >> + writel(val, port->base + RP_ECTL_6_R2); > There are nice macros that help with this nowadays. See the FIELD_* > macros in include/linux/bitfield.h. However, the above is consistent > with the rest of the driver, so feel free to leave this as-is. I will leave it as-is to be inline with rest of the driver. >> +} >> + >> static void tegra_pcie_port_enable(struct tegra_pcie_port *port) >> { >> unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); >> @@ -517,6 +602,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) >> } >> >> tegra_pcie_enable_rp_features(port); >> + if (soc->ectl.enable) > An empty line above would help declutter this. I will take care of it in V2 > >> + tegra_pcie_program_ectl_settings(port); >> } >> >> static void tegra_pcie_port_disable(struct tegra_pcie_port *port) >> @@ -2229,6 +2316,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { >> .has_gen2 = false, >> .force_pca_enable = false, >> .program_uphy = true, >> + .ectl.enable = false, >> }; >> >> static const struct tegra_pcie_port_soc tegra30_pcie_ports[] = { >> @@ -2252,6 +2340,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { >> .has_gen2 = false, >> .force_pca_enable = false, >> .program_uphy = true, >> + .ectl.enable = false, >> }; >> >> static const struct tegra_pcie_soc tegra124_pcie = { >> @@ -2268,6 +2357,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { >> .has_gen2 = true, >> .force_pca_enable = false, >> .program_uphy = true, >> + .ectl.enable = false, >> }; >> >> static const struct tegra_pcie_soc tegra210_pcie = { >> @@ -2284,6 +2374,15 @@ static const struct tegra_pcie_soc tegra210_pcie = { >> .has_gen2 = true, >> .force_pca_enable = true, >> .program_uphy = true, >> + .ectl.regs.rp_ectl_2_r1 = 0x0000000f, >> + .ectl.regs.rp_ectl_4_r1 = 0x00000067, >> + .ectl.regs.rp_ectl_5_r1 = 0x55010000, >> + .ectl.regs.rp_ectl_6_r1 = 0x00000001, >> + .ectl.regs.rp_ectl_2_r2 = 0x0000008f, >> + .ectl.regs.rp_ectl_4_r2 = 0x000000c7, >> + .ectl.regs.rp_ectl_5_r2 = 0x55010000, >> + .ectl.regs.rp_ectl_6_r2 = 0x00000001, >> + .ectl.enable = true, > This should be: > > .ectl = { > .regs = { > ... > } > .enable = true; > }, > > Do these parameters never differ between board layouts? Are they really > fixed per SoC generation? > > Thierry Till now all Tegra210 platform have same UPHY settings. They can differ if some components like MUX are added in UPHY routing, but I haven't seen such platforms with Tegra210.