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Sun, 20 Jun 2021 13:35:51 +0000 Received: from [10.25.74.204] (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 20 Jun 2021 13:35:47 +0000 Subject: Re: Query regarding the use of pcie-designware-plat.c file To: Jon Hunter , Bjorn Helgaas CC: , , , , , , , Thierry Reding , Krishna Thota , , References: <20210615194209.GA2908457@bjorn-Precision-5520> <10a92c35-6e4d-0428-079c-7e98ff6e9414@nvidia.com> From: Vidya Sagar Message-ID: Date: Sun, 20 Jun 2021 19:05:45 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <10a92c35-6e4d-0428-079c-7e98ff6e9414@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b1a701e5-ae65-4916-58f6-08d933f05230 X-MS-TrafficTypeDiagnostic: CH0PR12MB5203: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2021 13:35:51.2514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1a701e5-ae65-4916-58f6-08d933f05230 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5203 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Given Rob's latest reply, I think Jon's patch addressed the issue in the correct way. And IIUC, I think this is how it should be for all Synopsys DesignWare implementations unless the implementation really claims that it can even work with the generic pcie-designware-plat.c file, otherwise it shouldn't contain 'snps,dw-pcie' compatibility string. IMHO, the addition of 'snps,dw-pcie' along with the respective platform specific compatibility string should be strictly restricted. I think this thread is considered to be concluded at this point. Thanks, Vidya Sagar On 6/16/2021 1:24 PM, Jon Hunter wrote: > External email: Use caution opening links or attachments > > > On 15/06/2021 20:42, Bjorn Helgaas wrote: >> On Wed, Jun 09, 2021 at 05:54:38PM +0100, Jon Hunter wrote: >>> >>> On 09/06/2021 17:30, Bjorn Helgaas wrote: >>>> On Wed, Jun 09, 2021 at 12:52:37AM +0530, Vidya Sagar wrote: >>>>> Hi, >>>>> I would like to know what is the use of pcie-designware-plat.c file. This >>>>> looks like a skeleton file and can't really work with any specific hardware >>>>> as such. >>>>> Some context for this mail thread is, if the config CONFIG_PCIE_DW_PLAT is >>>>> enabled in a system where a Synopsys DesignWare IP based PCIe controller is >>>>> present and its configuration is enabled (Ex:- Tegra194 system with >>>>> CONFIG_PCIE_TEGRA194_HOST enabled), then, it can so happen that the probe of >>>>> pcie-designware-plat.c called first (because all DWC based PCIe controller >>>>> nodes have "snps,dw-pcie" compatibility string) and can crash the system. >>>> >>>> What's the crash? If a device claims to be compatible with >>>> "snps,dw-pcie" and pcie-designware-plat.c claims to know how to >>>> operate "snps,dw-pcie" devices, it seems like something is wrong. >>>> >>>> "snps,dw-pcie" is a generic device type, so pcie-designware-plat.c >>>> might not know how to operate device-specific details of some of those >>>> devices, but basic functionality should work and it certainly >>>> shouldn't crash. >>> >>> It is not really a crash but a hang when trying to access the hardware >>> before it has been properly initialised. >> >> This doesn't really answer my question. >> >> If the hardware claims to be compatible with "snps,dw-pcie" and a >> driver knows how to operate "snps,dw-pcie" devices, it should work. >> >> If the hardware requires initialization that is not part of the >> "snps,dw-pcie" programming model, it should not claim to be compatible >> with "snps,dw-pcie". Or, if pcie-designware-plat.c is missing some >> init that *is* part of the programming model, maybe it needs to be >> enhanced? > > Right and this is exactly why I removed the compatible string > "snps,dw-pcie" for Tegra194 because it is clear that this does not work > and hence not compatible. > > Sagar is purely trying to understand if this is case of other devices as > well or just Tegra194. > > Jon > > -- > nvpublic >