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* [PATCH v2] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
@ 2019-04-09 12:11 Marc Gonzalez
  2019-04-11  8:50 ` [PATCH v3] " Marc Gonzalez
  0 siblings, 1 reply; 6+ messages in thread
From: Marc Gonzalez @ 2019-04-09 12:11 UTC (permalink / raw)
  To: Bjorn Andersson; +Cc: Jeffrey Hugo, Vivek Gautam, Stanimir Varbanov, MSM, PCI

Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
---
Changes from v1:
	Drop SMMU patch from series (spun off, required)
	Drop PCIE20_PARF_BDF_TRANSLATE_N patch (AR8151 now works without it)
	Provide link to the original DTS in commit log
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 78 +++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f807ea3e2c6e..f848d9f2df2d 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -621,6 +621,84 @@
 				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 		};
 
+		pcie0: pci@1c00000 {
+			compatible = "qcom,pcie-msm8996";
+			reg-names = "parf", "dbi", "elbi", "config";
+			reg =	<0x01c00000 0x2000>,
+				<0x1b000000 0xf1d>,
+				<0x1b000f20 0xa8>,
+				<0x1b100000 0x100000>;
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			num-lanes = <1>;
+			phy-names = "pciephy";
+			phys = <&pciephy>;
+
+			ranges =
+			/*** downstream I/O ***/
+			<0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
+			/*** non-prefetchable memory ***/
+			<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
+
+			#interrupt-cells = <1>;
+			interrupt-names = "msi";
+			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map =
+				<0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, /* #INTA */
+				<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, /* #INTB */
+				<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, /* #INTC */
+				<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; /* #INTD */
+
+			clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
+			clocks =
+				<&gcc GCC_PCIE_0_PIPE_CLK>,
+				<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				<&gcc GCC_PCIE_0_AUX_CLK>;
+
+			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
+
+			/* PCIe Fundamental Reset */
+			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+		};
+
+		phy@1c06000 {
+			compatible = "qcom,msm8998-qmp-pcie-phy";
+			reg = <0x01c06000 0x18c>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clock-names = "aux", "cfg_ahb", "ref";
+			clocks =
+				<&gcc GCC_PCIE_PHY_AUX_CLK>,
+				<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				<&gcc GCC_PCIE_CLKREF_CLK>;
+
+			reset-names = "phy", "common";
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
+
+			vdda-phy-supply = <&vreg_l1a_0p875>;
+			vdda-pll-supply = <&vreg_l2a_1p2>;
+
+			pciephy: lane@1c06800 {
+				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
+				#phy-cells = <0>;
+
+				clock-names = "pipe0";
+				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+				clock-output-names = "pcie_0_pipe_clk_src";
+				#clock-cells = <0>;
+			};
+		};
+
 		tcsr_mutex_regs: syscon@1f40000 {
 			compatible = "syscon";
 			reg = <0x1f40000 0x20000>;
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  2019-04-09 12:11 [PATCH v2] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes Marc Gonzalez
@ 2019-04-11  8:50 ` " Marc Gonzalez
  2019-04-11  9:23   ` Stanimir Varbanov
                     ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Marc Gonzalez @ 2019-04-11  8:50 UTC (permalink / raw)
  To: Bjorn Andersson, Stanimir Varbanov; +Cc: Jeffrey Hugo, Vivek Gautam, MSM, PCI

Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
---
Changes from v2:
	- Move all X-names props *after* corresponding X(s) prop
	- Drop comments
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 69 +++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f807ea3e2c6e..dab3333e21f4 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -621,6 +621,75 @@
 				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 		};
 
+		pcie0: pci@1c00000 {
+			compatible = "qcom,pcie-msm8996";
+			reg =	<0x01c00000 0x2000>,
+				<0x1b000000 0xf1d>,
+				<0x1b000f20 0xa8>,
+				<0x1b100000 0x100000>;
+			reg-names = "parf", "dbi", "elbi", "config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			num-lanes = <1>;
+			phys = <&pciephy>;
+			phy-names = "pciephy";
+
+			ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
+
+			#interrupt-cells = <1>;
+			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map =	<0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_AUX_CLK>;
+			clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
+			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+		};
+
+		phy@1c06000 {
+			compatible = "qcom,msm8998-qmp-pcie-phy";
+			reg = <0x01c06000 0x18c>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_CLKREF_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			vdda-phy-supply = <&vreg_l1a_0p875>;
+			vdda-pll-supply = <&vreg_l2a_1p2>;
+
+			pciephy: lane@1c06800 {
+				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+				clock-names = "pipe0";
+				clock-output-names = "pcie_0_pipe_clk_src";
+				#clock-cells = <0>;
+			};
+		};
+
 		tcsr_mutex_regs: syscon@1f40000 {
 			compatible = "syscon";
 			reg = <0x1f40000 0x20000>;
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  2019-04-11  8:50 ` [PATCH v3] " Marc Gonzalez
@ 2019-04-11  9:23   ` Stanimir Varbanov
  2019-04-11  9:46     ` Marc Gonzalez
  2019-04-11 14:55   ` Marc Gonzalez
  2019-06-17 15:53   ` Bjorn Andersson
  2 siblings, 1 reply; 6+ messages in thread
From: Stanimir Varbanov @ 2019-04-11  9:23 UTC (permalink / raw)
  To: Marc Gonzalez, Bjorn Andersson; +Cc: Jeffrey Hugo, Vivek Gautam, MSM, PCI

Hi Marc,

On 4/11/19 11:50 AM, Marc Gonzalez wrote:
> Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
> 
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> ---
> Changes from v2:
> 	- Move all X-names props *after* corresponding X(s) prop
> 	- Drop comments
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 69 +++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index f807ea3e2c6e..dab3333e21f4 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -621,6 +621,75 @@
>  				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
>  		};
>  
> +		pcie0: pci@1c00000 {
> +			compatible = "qcom,pcie-msm8996";
> +			reg =	<0x01c00000 0x2000>,
> +				<0x1b000000 0xf1d>,
> +				<0x1b000f20 0xa8>,
> +				<0x1b100000 0x100000>;
> +			reg-names = "parf", "dbi", "elbi", "config";
> +			device_type = "pci";
> +			linux,pci-domain = <0>;
> +			bus-range = <0x00 0xff>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			num-lanes = <1>;
> +			phys = <&pciephy>;
> +			phy-names = "pciephy";
> +
> +			ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
> +				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
> +
> +			#interrupt-cells = <1>;
> +			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi";
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map =	<0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_0_AUX_CLK>;
> +			clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
> +
> +			power-domains = <&gcc PCIE_0_GDSC>;
> +			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
> +			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;

where are pinctrl properties? Probably in board .dts files?


-- 
regards,
Stan

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  2019-04-11  9:23   ` Stanimir Varbanov
@ 2019-04-11  9:46     ` Marc Gonzalez
  0 siblings, 0 replies; 6+ messages in thread
From: Marc Gonzalez @ 2019-04-11  9:46 UTC (permalink / raw)
  To: Stanimir Varbanov, Bjorn Andersson; +Cc: Jeffrey Hugo, Vivek Gautam, MSM, PCI

On 11/04/2019 11:23, Stanimir Varbanov wrote:

> On 4/11/19 11:50 AM, Marc Gonzalez wrote:
> 
>> +			power-domains = <&gcc PCIE_0_GDSC>;
>> +			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
>> +			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
> 
> Where are pinctrl properties? Probably in board .dts files?

I didn't define any; they appear to be optional.

I have checked that PCIe Fundamental Reset works as expected.

Regards.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  2019-04-11  8:50 ` [PATCH v3] " Marc Gonzalez
  2019-04-11  9:23   ` Stanimir Varbanov
@ 2019-04-11 14:55   ` Marc Gonzalez
  2019-06-17 15:53   ` Bjorn Andersson
  2 siblings, 0 replies; 6+ messages in thread
From: Marc Gonzalez @ 2019-04-11 14:55 UTC (permalink / raw)
  To: Bjorn Andersson, Stanimir Varbanov, Rob Herring, Mark Rutland,
	Robin Murphy
  Cc: Jeffrey Hugo, Vivek Gautam, MSM, PCI

+robh, +mrutland for DT, +rmurphy for PCI

On 11/04/2019 10:50, Marc Gonzalez wrote:

> Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
> 
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> ---
> Changes from v2:
> 	- Move all X-names props *after* corresponding X(s) prop
> 	- Drop comments
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 69 +++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index f807ea3e2c6e..dab3333e21f4 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -621,6 +621,75 @@
>  				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
>  		};
>  
> +		pcie0: pci@1c00000 {
> +			compatible = "qcom,pcie-msm8996";
> +			reg =	<0x01c00000 0x2000>,
> +				<0x1b000000 0xf1d>,
> +				<0x1b000f20 0xa8>,
> +				<0x1b100000 0x100000>;
> +			reg-names = "parf", "dbi", "elbi", "config";
> +			device_type = "pci";
> +			linux,pci-domain = <0>;
> +			bus-range = <0x00 0xff>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			num-lanes = <1>;
> +			phys = <&pciephy>;
> +			phy-names = "pciephy";
> +
> +			ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
> +				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
> +
> +			#interrupt-cells = <1>;
> +			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi";
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map =	<0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_0_AUX_CLK>;
> +			clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
> +
> +			power-domains = <&gcc PCIE_0_GDSC>;
> +			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
> +			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		phy@1c06000 {
> +			compatible = "qcom,msm8998-qmp-pcie-phy";
> +			reg = <0x01c06000 0x18c>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_CLKREF_CLK>;
> +			clock-names = "aux", "cfg_ahb", "ref";
> +
> +			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
> +			reset-names = "phy", "common";
> +
> +			vdda-phy-supply = <&vreg_l1a_0p875>;
> +			vdda-pll-supply = <&vreg_l2a_1p2>;
> +
> +			pciephy: lane@1c06800 {
> +				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
> +				#phy-cells = <0>;
> +
> +				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> +				clock-names = "pipe0";
> +				clock-output-names = "pcie_0_pipe_clk_src";
> +				#clock-cells = <0>;
> +			};
> +		};
> +
>  		tcsr_mutex_regs: syscon@1f40000 {
>  			compatible = "syscon";
>  			reg = <0x1f40000 0x20000>;

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  2019-04-11  8:50 ` [PATCH v3] " Marc Gonzalez
  2019-04-11  9:23   ` Stanimir Varbanov
  2019-04-11 14:55   ` Marc Gonzalez
@ 2019-06-17 15:53   ` Bjorn Andersson
  2 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-06-17 15:53 UTC (permalink / raw)
  To: Marc Gonzalez; +Cc: Stanimir Varbanov, Jeffrey Hugo, Vivek Gautam, MSM, PCI

On Thu 11 Apr 01:50 PDT 2019, Marc Gonzalez wrote:

> Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
> 
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>

Applied

Thanks,
Bjorn

> ---
> Changes from v2:
> 	- Move all X-names props *after* corresponding X(s) prop
> 	- Drop comments
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 69 +++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index f807ea3e2c6e..dab3333e21f4 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -621,6 +621,75 @@
>  				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
>  		};
>  
> +		pcie0: pci@1c00000 {
> +			compatible = "qcom,pcie-msm8996";
> +			reg =	<0x01c00000 0x2000>,
> +				<0x1b000000 0xf1d>,
> +				<0x1b000f20 0xa8>,
> +				<0x1b100000 0x100000>;
> +			reg-names = "parf", "dbi", "elbi", "config";
> +			device_type = "pci";
> +			linux,pci-domain = <0>;
> +			bus-range = <0x00 0xff>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			num-lanes = <1>;
> +			phys = <&pciephy>;
> +			phy-names = "pciephy";
> +
> +			ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
> +				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
> +
> +			#interrupt-cells = <1>;
> +			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi";
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map =	<0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_0_AUX_CLK>;
> +			clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
> +
> +			power-domains = <&gcc PCIE_0_GDSC>;
> +			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
> +			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		phy@1c06000 {
> +			compatible = "qcom,msm8998-qmp-pcie-phy";
> +			reg = <0x01c06000 0x18c>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_CLKREF_CLK>;
> +			clock-names = "aux", "cfg_ahb", "ref";
> +
> +			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
> +			reset-names = "phy", "common";
> +
> +			vdda-phy-supply = <&vreg_l1a_0p875>;
> +			vdda-pll-supply = <&vreg_l2a_1p2>;
> +
> +			pciephy: lane@1c06800 {
> +				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
> +				#phy-cells = <0>;
> +
> +				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> +				clock-names = "pipe0";
> +				clock-output-names = "pcie_0_pipe_clk_src";
> +				#clock-cells = <0>;
> +			};
> +		};
> +
>  		tcsr_mutex_regs: syscon@1f40000 {
>  			compatible = "syscon";
>  			reg = <0x1f40000 0x20000>;
> -- 
> 2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-09 12:11 [PATCH v2] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes Marc Gonzalez
2019-04-11  8:50 ` [PATCH v3] " Marc Gonzalez
2019-04-11  9:23   ` Stanimir Varbanov
2019-04-11  9:46     ` Marc Gonzalez
2019-04-11 14:55   ` Marc Gonzalez
2019-06-17 15:53   ` Bjorn Andersson

Linux-PCI Archive on lore.kernel.org

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