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[188.155.201.27]) by smtp.googlemail.com with ESMTPSA id hs12-20020a1709073e8c00b006dfdfdac005sm5836373ejc.174.2022.03.28.04.40.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Mar 2022 04:40:13 -0700 (PDT) Message-ID: Date: Mon, 28 Mar 2022 13:40:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver Content-Language: en-US To: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" Cc: "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" , =?UTF-8?B?7KCE66y46riw?= References: <564c7092-d6a3-7766-d83f-9762075d055f@kernel.org> <0716d9e4-24e1-d16c-162c-00a8664296e1@kernel.org> <20220328014430epcms2p7063834feb0abdf2f38a62723c96c9ff1@epcms2p7> <20220328090200epcms2p8637d2a2e09a3a627be776586b80c8adf@epcms2p8> <20220328112918epcms2p44bfdd6ef74c14f04bae6a475054860b6@epcms2p4> From: Krzysztof Kozlowski In-Reply-To: <20220328112918epcms2p44bfdd6ef74c14f04bae6a475054860b6@epcms2p4> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 28/03/2022 13:29, 이왕석 wrote: >> --------- Original Message --------- >> Sender : Krzysztof Kozlowski  >> Date : 2022-03-28 18:38 (GMT+9) >> Title : Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver >> >> On 28/03/2022 11:02, 이왕석 wrote: >>>>  --------- Original Message --------- >>>>  Sender : Krzysztof Kozlowski  >>>>  Date : 2022-03-28 16:12 (GMT+9) >>>>  Title : Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver >>>> >>>>  On 28/03/2022 03:44, 이왕석 wrote: >>>>>   This series patches include newly PCIe support for Axis ARTPEC-8 SoC. >>>>>   ARTPEC-8 is the SoC platform of Axis Communications. >>>>>   PCIe controller driver and phy driver have been newly added. >>>>>   There is also a new MAINTAINER in the addition of phy driver. >>>>>   PCIe controller is designed based on Design-Ware PCIe controller IP >>>>>   and PCIe phy is desinged based on SAMSUNG PHY IP. >>>>>   It also includes modifications to the Design-Ware controller driver to  >>>>>   run the 64bit-based ARTPEC-8 PCIe controller driver. >>>>>   It consists of 6 patches in total. >>>>>    >>>>>   This series has been tested on AXIS SW bring-up board  >>>>>   with ARTPEC-8 chipset. >>>> >>>>  You lost mail threading. This makes reading this difficult for us. Plus >>>>  you sent something non-applicable (patch #2), so please resend. >>>> >>>>  Knowing recent Samsung reluctance to extend existing drivers and always >>>>  duplicate, please provide description/analysis why this driver cannot be >>>>  combined with existing driver. The answer like: we need several syscon >>>>  because we do not implement other frameworks (like interconnect) are not >>>>  valid. >>>> >>>>  Best regards, >>>>  Krzysztof >>>   >>>  Hello, Krzysztof >>>  Thanks for your review. >>>   >>>  patch#2 was sent to the wrong format so sent again. >>>  Sorry for causing confusion. >>   >> The first sending was HTML. Second was broken text, so still not working. >> >> Please resend everything with proper threading. > > Hello, Krzysztof > > I sent patch#2 three times. > due to the influence of the email system, > there was something wrong with the first and second mails. > Sorry for causing confusion. > Did you receive the third patch i sent you? Maybe, I don't know. It's not threaded so it's difficult to find it among other 100 emails... > >>>  This patch is specialized in Artpec-8,  >>>  the SoC Platform of Axis Communication, and is newly applied. >>>  Since the target SoC platform is different from the driver previously  >>>  used by Samsung, it is difficult to merge with the existing driver. >> >> Recently I always saw such answers and sometimes it was true, sometimes >> not. What is exactly different? >> >> Best regards, >> Krzysztof > > The main reason this patch should be added is that > this patch is not the driver applied to exynos platform. Still this does not explain why you need separate driver. > Because the SoC platform is different, > the IP configuration of PCIe is also different. What is exactly different? Usually drivers can support IP blocks with some differences... > We will organize a driver for Artpec-8 platform and > if there is no special reason, maintain this > without adding it from the next series. I don't understand this. Best regards, Krzysztof