From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B6DC433FE for ; Thu, 3 Nov 2022 03:40:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbiKCDkT (ORCPT ); Wed, 2 Nov 2022 23:40:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbiKCDkS (ORCPT ); Wed, 2 Nov 2022 23:40:18 -0400 X-Greylist: delayed 1026 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Wed, 02 Nov 2022 20:40:16 PDT Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34BF11571F for ; Wed, 2 Nov 2022 20:40:15 -0700 (PDT) X-ASG-Debug-ID: 1667445785-086e235325630c0001-i5rUwQ Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx1.zhaoxin.com with ESMTP id 4H8CKghlSEVnENGS (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 03 Nov 2022 11:23:05 +0800 (CST) X-Barracuda-Envelope-From: SilviaZhao-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXBJMBX02.zhaoxin.com (10.29.252.6) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 3 Nov 2022 11:23:05 +0800 Received: from silvia-OptiPlex-3010.zhaoxin.com (10.29.8.47) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 3 Nov 2022 11:23:04 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: silviazhao-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.6 To: , , , , , , , , , , , , , CC: , , Subject: [PATCH] x86/perf: Fixed kernel panic during boot on Nano processor. Date: Thu, 3 Nov 2022 11:23:04 +0800 X-ASG-Orig-Subj: [PATCH] x86/perf: Fixed kernel panic during boot on Nano processor. Message-ID: <20221103032304.27753-1-silviazhao-oc@zhaoxin.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.47] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1667445785 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1332 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0007 1.0000 -2.0164 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.101869 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Nano processor may not fully support rdpmc instruction, it works well for reading general pmc counter, but will lead GP(general protection) when accessing fixed pmc counter. Furthermore, family/mode information is same between Nano processor and ZX-C processor, it leads to zhaoxin pmu driver is wrongly loaded for Nano processor, which resulting boot kernal fail. To solve this problem, stepping information will be checked to distinguish between Nano processor and ZX-C processor. [https://bugzilla.kernel.org/show_bug.cgi?id=212389] Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com> Signed-off-by: silviazhao-oc --- arch/x86/events/zhaoxin/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 949d845c922b..cef1de251613 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -541,7 +541,8 @@ __init int zhaoxin_pmu_init(void) switch (boot_cpu_data.x86) { case 0x06: - if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) { + if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) || + boot_cpu_data.x86_model == 0x19) { x86_pmu.max_period = x86_pmu.cntval_mask >> 1; -- 2.17.1