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X-CSE-ConnectionGUID: gNngCGD/R2KaO1nj2A1zVw== X-CSE-MsgGUID: D2jLTxB3SM6YanerxoLrgA== X-IronPort-AV: E=McAfee;i="6600,9927,11041"; a="12197661" X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="12197661" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 22:57:56 -0700 X-CSE-ConnectionGUID: 1KuqrSs2RDat7Er/1WVpHg== X-CSE-MsgGUID: 8iIV9R12Si+eflAuqF5r4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,195,1708416000"; d="scan'208";a="52299881" Received: from xiongzha-mobl1.ccr.corp.intel.com (HELO [10.124.244.162]) ([10.124.244.162]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2024 22:57:50 -0700 Message-ID: <41c6af10-82f8-4e67-9d55-6034ad079418@linux.intel.com> Date: Fri, 12 Apr 2024 13:57:47 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 06/41] perf: x86: Add function to switch PMI handler Content-Language: en-US To: Sean Christopherson Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-7-xiong.y.zhang@linux.intel.com> From: "Zhang, Xiong Y" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/12/2024 3:17 AM, Sean Christopherson wrote: > On Fri, Jan 26, 2024, Xiong Zhang wrote: >> From: Xiong Zhang >> >> Add function to switch PMI handler since passthrough PMU and host PMU will >> use different interrupt vectors. >> >> Signed-off-by: Xiong Zhang >> Signed-off-by: Mingwei Zhang >> --- >> arch/x86/events/core.c | 15 +++++++++++++++ >> arch/x86/include/asm/perf_event.h | 3 +++ >> 2 files changed, 18 insertions(+) >> >> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c >> index 40ad1425ffa2..3f87894d8c8e 100644 >> --- a/arch/x86/events/core.c >> +++ b/arch/x86/events/core.c >> @@ -701,6 +701,21 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) >> } >> EXPORT_SYMBOL_GPL(perf_guest_get_msrs); >> >> +void perf_guest_switch_to_host_pmi_vector(void) >> +{ >> + lockdep_assert_irqs_disabled(); >> + >> + apic_write(APIC_LVTPC, APIC_DM_NMI); >> +} >> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_host_pmi_vector); >> + >> +void perf_guest_switch_to_kvm_pmi_vector(void) >> +{ >> + lockdep_assert_irqs_disabled(); >> + >> + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_VPMU_VECTOR); >> +} >> +EXPORT_SYMBOL_GPL(perf_guest_switch_to_kvm_pmi_vector); > > Why slice and dice the context switch if it's all in perf? Just do this in > perf_guest_enter(). > As perf_guest_enter() is in perf core which manages all PMUs, while switch_pmi_vector is for x86 core PMU only, so switch_pmi_vector is put in x86 pmu driver. pmu driver can call perf core function directly, perf core manage pmu through pmu->ops and pmu->flags. If switch_pmi_vector is called in perf_guest_enter, extra interfaces will be added into pmu->ops, this impacts other PMU driver.