* [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support
@ 2023-03-24 17:13 Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 1/5] cxl: Add function to count regblocks of a given type Jonathan Cameron
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
Significant changes since v1:
- New patch 2 - allow a PMU device to have a parent. This helps identify
the association of the CPMU with the CXL devices without needing to
rely on messy naming of the PMU.
- Set the parent for each CPMU instance.
- Add missing cpmu.h from patch 3.
- Fix a bug due to bad ordering of ida allocation wrt to device_initialize()
- Split the event list in two as handling for fixed and configurable
counters is different. Add util functions to search each list.
- Lots of other improvements in patch 4 called out in that patch description.
Thanks to all those who looked at it, and Kan Liang in particular for
all the feedback on the main driver.
Updated cover letter.
The CXL rev 3.0 specification introduces a CXL Performance Monitoring
Unit definition. CXL components may have any number of these blocks. The
definition is highly flexible, but that does bring complexity in the
driver.
Notes.
1) The QEMU model against which this was developed needs tidying up.
Latest tree at https://gitlab.com/jic23/qemu branch cxl-2023-02-28
It's backed up behind other series that I plan to upstream first.
2) There are quite a lot of corner cases that will need working through
with variants of the model, or I'll have to design a pathological
set of CPMUs to hit all the corner cases in one go. So whilst I believe
the driver should be fine for what it supports we may find issues
as those corners of what is allowed are explored.
3) I'm not sure it makes sense to hang this of the cxl/pci driver but
couldn't really figure out where else in the current structure we could
make it fit cleanly.
4) Driver location. In past perf maintainers have requested perf drivers
for PCI etc be under drivers/perf. That would require moving some
CXL headers to be more generally visible, but is certainly possible
if there is agreement between CXL and perf maintainers on the correct
location.
5) Patch 1 led to a discussion of how to handle the self describing
and extensible nature of the CPMU counters. That is likely to involve
a description in the "caps" sysfs directory and perf tool code that is
aware of the different event combinations that make sense and can
establish which sets are available on a given device.
That is likely to take a while to converge on, so as the driver is useful
in the current state, I'm looking to upstream this first and deal with
the more complex handling later.
6) There is a lot of other functionality that can be added in future
include allowing for simpler hardware implementations that may not
support the minimum level of features currently required by the driver
(freeze, overflow interrupts etc).
CXL rev 3.0 specification available from https://www.computeexpresslink.org
Jonathan Cameron (5):
cxl: Add function to count regblocks of a given type.
perf: Allow a PMU to have a parent.
cxl/pci: Find and register CXL PMU devices
cxl: CXL Performance Monitoring Unit driver
docs: perf: Minimal introduction the the CXL PMU device and driver.
Documentation/admin-guide/perf/cxl.rst | 65 ++
Documentation/admin-guide/perf/index.rst | 1 +
drivers/cxl/Kconfig | 12 +
drivers/cxl/Makefile | 1 +
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 3 +
drivers/cxl/core/cpmu.c | 72 ++
drivers/cxl/core/pci.c | 2 +-
drivers/cxl/core/port.c | 4 +-
drivers/cxl/core/regs.c | 50 +-
drivers/cxl/cpmu.c | 937 +++++++++++++++++++++++
drivers/cxl/cpmu.h | 56 ++
drivers/cxl/cxl.h | 17 +-
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/pci.c | 27 +-
include/linux/perf_event.h | 1 +
kernel/events/core.c | 1 +
17 files changed, 1243 insertions(+), 8 deletions(-)
create mode 100644 Documentation/admin-guide/perf/cxl.rst
create mode 100644 drivers/cxl/core/cpmu.c
create mode 100644 drivers/cxl/cpmu.c
create mode 100644 drivers/cxl/cpmu.h
--
2.37.2
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/5] cxl: Add function to count regblocks of a given type.
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
@ 2023-03-24 17:13 ` Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 2/5] perf: Allow a PMU to have a parent Jonathan Cameron
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
Until the recently release CXL 3.0 specification, there
was only ever one instance of any given register block pointed
to by the Register Block Locator DVSEC. Now, the specification allows
for multiple CXL PMU instances, each with their own register block.
To enable this add an index parameter to cxl_find_regblock()
and use that to implement cxl_count_regblock().
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v2:
Gathered tags.
---
drivers/cxl/core/pci.c | 2 +-
drivers/cxl/core/port.c | 2 +-
drivers/cxl/core/regs.c | 34 +++++++++++++++++++++++++++++++---
drivers/cxl/cxl.h | 3 ++-
drivers/cxl/pci.c | 2 +-
5 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 7328a2552411..c90251f60771 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -50,7 +50,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
&lnkcap))
return 0;
- rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
if (rc)
dev_dbg(&port->dev, "failed to find component registers\n");
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 8ee6b6e2e2a4..97cc03dbceee 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1333,7 +1333,7 @@ static resource_size_t find_component_registers(struct device *dev)
pdev = to_pci_dev(dev);
- cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
return map.resource;
}
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 1476a0299c9b..7389dd1af967 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -290,6 +290,7 @@ static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi,
* @pdev: The CXL PCI device to enumerate.
* @type: Register Block Indicator id
* @map: Enumeration output, clobbered on error
+ * @index: Index into which particular instance of a regblock we want.
*
* Return: 0 if register block enumerated, negative error code otherwise
*
@@ -297,9 +298,10 @@ static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi,
* by @type.
*/
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map)
+ struct cxl_register_map *map, int index)
{
u32 regloc_size, regblocks;
+ int instance = 0;
int regloc, i;
map->resource = CXL_RESOURCE_NONE;
@@ -323,8 +325,11 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
if (!cxl_decode_regblock(pdev, reg_lo, reg_hi, map))
continue;
- if (map->reg_type == type)
- return 0;
+ if (map->reg_type == type) {
+ if (index == instance)
+ return 0;
+ instance++;
+ }
}
map->resource = CXL_RESOURCE_NONE;
@@ -332,6 +337,29 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
}
EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
+/**
+ * cxl_count_regblock() - Count instances of a given regblock type.
+ * @pdev: The CXL PCI device to enumerate.
+ * @type: Register Block Indicator id
+ *
+ * Some regblocks may be repeated. Count how many instances.
+ *
+ * Return: count of matching regblocks.
+ */
+int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
+{
+ struct cxl_register_map map;
+ int rc, count = 0;
+
+ while (1) {
+ rc = cxl_find_regblock(pdev, type, &map, count);
+ if (rc)
+ return count;
+ count++;
+ }
+}
+EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
+
resource_size_t cxl_rcrb_to_component(struct device *dev,
resource_size_t rcrb,
enum cxl_rcrb which)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index aab87d74474d..0cc33e2a99d7 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -260,8 +260,9 @@ int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
struct cxl_register_map *map);
enum cxl_regloc_type;
+int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map);
+ struct cxl_register_map *map, int index);
enum cxl_rcrb {
CXL_RCRB_DOWNSTREAM,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 60b23624d167..74443a5c3cc8 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -343,7 +343,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
{
int rc;
- rc = cxl_find_regblock(pdev, type, map);
+ rc = cxl_find_regblock(pdev, type, map, 0);
if (rc)
return rc;
--
2.37.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 1/5] cxl: Add function to count regblocks of a given type Jonathan Cameron
@ 2023-03-24 17:13 ` Jonathan Cameron
2023-03-27 17:04 ` Liang, Kan
2023-03-24 17:13 ` [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
Some PMUs have well defined parents such as PCI devices.
As the device_initialize() and device_add() are all within
pmu_dev_alloc() which is called from perf_pmu_register()
there is no opportunity to set the parent from within a driver.
Add a struct device *parent field to struct pmu and use that
to set the parent.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/linux/perf_event.h | 1 +
kernel/events/core.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index d5628a7b5eaa..b99db1eda72c 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -303,6 +303,7 @@ struct pmu {
struct module *module;
struct device *dev;
+ struct device *parent;
const struct attribute_group **attr_groups;
const struct attribute_group **attr_update;
const char *name;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index fb3e436bcd4a..a84c282221f2 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11367,6 +11367,7 @@ static int pmu_dev_alloc(struct pmu *pmu)
dev_set_drvdata(pmu->dev, pmu);
pmu->dev->bus = &pmu_bus;
+ pmu->dev->parent = pmu->parent;
pmu->dev->release = pmu_dev_release;
ret = dev_set_name(pmu->dev, "%s", pmu->name);
--
2.37.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 1/5] cxl: Add function to count regblocks of a given type Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 2/5] perf: Allow a PMU to have a parent Jonathan Cameron
@ 2023-03-24 17:13 ` Jonathan Cameron
2023-03-24 21:01 ` kernel test robot
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
4 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
CXL PMU devices can be found from entries in the Register
Locator DVSEC.
In order to register the minimum number of IRQ vectors necessary
to support all CPMUs found, separate the registration into two
steps. First find the devices, and query the IRQs used and then
register the devices. Between these two steps, request the
IRQ vectors necessary and enable bus master support.
Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
follow a similar pattern the number of vectors necessary is known
before any parts of the driver stack rely on their availability.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v2:
- Add missing cpmu.h
- Fix free of unallocated ida by reordering that to be before
device_initialize(). (Thanks to Davidlohr)
---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 3 ++
drivers/cxl/core/cpmu.c | 72 +++++++++++++++++++++++++++++++++++++++
drivers/cxl/core/port.c | 2 ++
drivers/cxl/core/regs.c | 16 +++++++++
drivers/cxl/cpmu.h | 56 ++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 14 ++++++++
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/pci.c | 25 +++++++++++++-
9 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index ca4ae31d8f57..45e5543aff52 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -12,5 +12,6 @@ cxl_core-y += memdev.o
cxl_core-y += mbox.o
cxl_core-y += pci.o
cxl_core-y += hdm.o
+cxl_core-y += cpmu.o
cxl_core-$(CONFIG_TRACING) += trace.o
cxl_core-$(CONFIG_CXL_REGION) += region.o
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index cde475e13216..05e18fed3a75 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -17,12 +17,14 @@ extern struct device_attribute dev_attr_region;
extern const struct device_type cxl_pmem_region_type;
extern const struct device_type cxl_dax_region_type;
extern const struct device_type cxl_region_type;
+extern const struct device_type cxl_cpmu_type;
void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
#define CXL_REGION_TYPE(x) (&cxl_region_type)
#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
+#define CXL_CPMU_TYPE(x) (&cxl_cpmu_region_type)
int cxl_region_init(void);
void cxl_region_exit(void);
#else
@@ -41,6 +43,7 @@ static inline void cxl_region_exit(void)
#define SET_CXL_REGION_ATTR(x)
#define CXL_PMEM_REGION_TYPE(x) NULL
#define CXL_DAX_REGION_TYPE(x) NULL
+#define CXL_CPMU_TYPE(x) NULL
#endif
struct cxl_send_command;
diff --git a/drivers/cxl/core/cpmu.c b/drivers/cxl/core/cpmu.c
new file mode 100644
index 000000000000..8aff35055c05
--- /dev/null
+++ b/drivers/cxl/core/cpmu.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2022 Huawei. All rights reserved. */
+
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/idr.h>
+#include <cxlmem.h>
+#include <cpmu.h>
+#include <cxl.h>
+#include "core.h"
+
+static DEFINE_IDA(cpmu_ida);
+
+static void cxl_cpmu_release(struct device *dev)
+{
+ struct cxl_cpmu *cpmu = container_of(dev, struct cxl_cpmu, dev);
+
+ ida_free(&cpmu_ida, cpmu->id);
+ kfree(cpmu);
+}
+
+const struct device_type cxl_cpmu_type = {
+ .name = "cxl_cpmu",
+ .release = cxl_cpmu_release,
+};
+
+static void remove_dev(void *dev)
+{
+ device_del(dev);
+}
+
+int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int index)
+{
+ struct cxl_cpmu *cpmu;
+ struct device *dev;
+ int rc;
+
+ cpmu = kzalloc(sizeof(*cpmu), GFP_KERNEL);
+ if (!cpmu)
+ return -ENOMEM;
+
+ rc = ida_alloc(&cpmu_ida, GFP_KERNEL);
+ if (rc < 0) {
+ kfree(cpmu);
+ return rc;
+ }
+ cpmu->id = rc;
+
+ cpmu->base = regs->cpmu;
+ dev = &cpmu->dev;
+ device_initialize(dev);
+ device_set_pm_not_required(dev);
+ dev->parent = parent;
+ dev->bus = &cxl_bus_type;
+ dev->type = &cxl_cpmu_type;
+
+ rc = dev_set_name(dev, "cpmu%d", cpmu->id);
+ if (rc)
+ goto err;
+
+ rc = device_add(dev);
+ if (rc)
+ goto err;
+
+ return devm_add_action_or_reset(parent, remove_dev, dev);
+
+err:
+ put_device(&cpmu->dev);
+ return rc;
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_cpmu_add, CXL);
+
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 97cc03dbceee..2154bf8d2aad 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -57,6 +57,8 @@ static int cxl_device_id(const struct device *dev)
return CXL_DEVICE_MEMORY_EXPANDER;
if (dev->type == CXL_REGION_TYPE())
return CXL_DEVICE_REGION;
+ if (dev->type == &cxl_cpmu_type)
+ return CXL_DEVICE_CPMU;
return 0;
}
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 7389dd1af967..99d6ebe3aba9 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -6,6 +6,7 @@
#include <linux/pci.h>
#include <cxlmem.h>
#include <cxlpci.h>
+#include <cpmu.h>
#include "core.h"
@@ -360,6 +361,21 @@ int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
}
EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
+int cxl_map_cpmu_regs(struct pci_dev *pdev, struct cxl_cpmu_regs *regs,
+ struct cxl_register_map *map)
+{
+ struct device *dev = &pdev->dev;
+ resource_size_t phys_addr;
+
+ phys_addr = map->resource;
+ regs->cpmu = devm_cxl_iomap_block(dev, phys_addr, CPMU_REGMAP_SIZE);
+ if (!regs->cpmu)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_map_cpmu_regs, CXL);
+
resource_size_t cxl_rcrb_to_component(struct device *dev,
resource_size_t rcrb,
enum cxl_rcrb which)
diff --git a/drivers/cxl/cpmu.h b/drivers/cxl/cpmu.h
new file mode 100644
index 000000000000..2cf78a6b9b13
--- /dev/null
+++ b/drivers/cxl/cpmu.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright(c) 2022 Huawei
+ * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
+ */
+#ifndef CXL_CPMU_H
+#define CXL_CPMU_H
+
+#define CPMU_CAP_REG 0x0
+#define CPMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0)
+#define CPMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8)
+#define CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20)
+#define CPMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32)
+#define CPMU_FILTER_HDM BIT(0)
+#define CPMU_FILTER_CHAN_RANK_BANK BIT(1)
+#define CPMU_CAP_MSI_N_MSK GENMASK_ULL(47, 44)
+#define CPMU_CAP_WRITEABLE_WHEN_FROZEN BIT_ULL(48)
+#define CPMU_CAP_FREEZE BIT_ULL(49)
+#define CPMU_CAP_INT BIT_ULL(50)
+#define CPMU_CAP_VERSION_MSK GENMASK_ULL(63, 60)
+
+#define CPMU_OVERFLOW_REG 0x10
+#define CPMU_FREEZE_REG 0x18
+#define CPMU_EVENT_CAP_REG(n) (0x100 + 8 * (n))
+#define CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK GENMASK_ULL(31, 0)
+#define CPMU_EVENT_CAP_GROUP_ID_MSK GENMASK_ULL(47, 32)
+#define CPMU_EVENT_CAP_VENDOR_ID_MSK GENMASK_ULL(63, 48)
+
+#define CPMU_COUNTER_CFG_REG(n) (0x200 + 8 * (n))
+#define CPMU_COUNTER_CFG_TYPE_MSK GENMASK_ULL(1, 0)
+#define CPMU_COUNTER_CFG_TYPE_FREE_RUN 0
+#define CPMU_COUNTER_CFG_TYPE_FIXED_FUN 1
+#define CPMU_COUNTER_CFG_TYPE_CONFIGURABLE 2
+#define CPMU_COUNTER_CFG_ENABLE BIT_ULL(8)
+#define CPMU_COUNTER_CFG_INT_ON_OVRFLW BIT_ULL(9)
+#define CPMU_COUNTER_CFG_FREEZE_ON_OVRFLW BIT_ULL(10)
+#define CPMU_COUNTER_CFG_EDGE BIT_ULL(11)
+#define CPMU_COUNTER_CFG_INVERT BIT_ULL(12)
+#define CPMU_COUNTER_CFG_THRESHOLD_MSK GENMASK_ULL(23, 16)
+#define CPMU_COUNTER_CFG_EVENTS_MSK GENMASK_ULL(55, 24)
+#define CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59)
+
+#define CPMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8))
+#define CPMU_FILTER_CFG_VALUE_MSK GENMASK(15, 0)
+
+#define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
+
+#define CPMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
+struct cxl_cpmu {
+ struct device dev;
+ void __iomem *base;
+ int id;
+};
+
+#define to_cxl_cpmu(dev) container_of(dev, struct cxl_cpmu, dev)
+#endif
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 0cc33e2a99d7..a7b8a0c46715 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -209,6 +209,10 @@ struct cxl_regs {
struct_group_tagged(cxl_device_regs, device_regs,
void __iomem *status, *mbox, *memdev;
);
+
+ struct_group_tagged(cxl_cpmu_regs, cpmu_regs,
+ void __iomem *cpmu;
+ );
};
struct cxl_reg_map {
@@ -229,6 +233,10 @@ struct cxl_device_reg_map {
struct cxl_reg_map memdev;
};
+struct cxl_cpmu_reg_map {
+ struct cxl_reg_map cpmu;
+};
+
/**
* struct cxl_register_map - DVSEC harvested register block mapping parameters
* @base: virtual base of the register-block-BAR + @block_offset
@@ -237,6 +245,7 @@ struct cxl_device_reg_map {
* @reg_type: see enum cxl_regloc_type
* @component_map: cxl_reg_map for component registers
* @device_map: cxl_reg_maps for device registers
+ * @cpmu_map: cxl_reg_maps for CXL Performance Monitoring Units
*/
struct cxl_register_map {
void __iomem *base;
@@ -246,6 +255,7 @@ struct cxl_register_map {
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
+ struct cxl_cpmu_reg_map cpmu_map;
};
};
@@ -258,6 +268,8 @@ int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
unsigned long map_mask);
int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
struct cxl_register_map *map);
+int cxl_map_cpmu_regs(struct pci_dev *pdev, struct cxl_cpmu_regs *regs,
+ struct cxl_register_map *map);
enum cxl_regloc_type;
int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
@@ -750,6 +762,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
#define CXL_DEVICE_REGION 6
#define CXL_DEVICE_PMEM_REGION 7
#define CXL_DEVICE_DAX_REGION 8
+#define CXL_DEVICE_CPMU 9
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
#define CXL_MODALIAS_FMT "cxl:t%d"
@@ -789,6 +802,7 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
}
#endif
+int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int idx);
/*
* Unit test builds overrides this to __weak, find the 'strong' version
* of these symbols in tools/testing/cxl/.
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index be6a2ef3cce3..2fd495ab3de1 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -65,6 +65,7 @@ enum cxl_regloc_type {
CXL_REGLOC_RBI_COMPONENT,
CXL_REGLOC_RBI_VIRT,
CXL_REGLOC_RBI_MEMDEV,
+ CXL_REGLOC_RBI_CPMU,
CXL_REGLOC_RBI_TYPES
};
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 74443a5c3cc8..e8bc36cc2724 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -704,7 +704,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
struct cxl_register_map map;
struct cxl_memdev *cxlmd;
struct cxl_dev_state *cxlds;
- int rc;
+ int i, rc, cpmu_count;
/*
* Double check the anonymous union trickery in struct cxl_regs
@@ -781,6 +781,29 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ cpmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_CPMU);
+ for (i = 0; i < cpmu_count; i++) {
+ struct cxl_cpmu_regs cpmu_regs;
+
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_CPMU, &map, i);
+ if (rc) {
+ dev_dbg(&pdev->dev, "Could not find CPMU regblock\n");
+ break;
+ }
+
+ rc = cxl_map_cpmu_regs(pdev, &cpmu_regs, &map);
+ if (rc) {
+ dev_dbg(&pdev->dev, "Could not map CPMU regs\n");
+ break;
+ }
+
+ rc = devm_cxl_cpmu_add(cxlds->dev, &cpmu_regs, i);
+ if (rc) {
+ dev_dbg(&pdev->dev, "Could not add CPMU instance\n");
+ break;
+ }
+ }
+
cxlmd = devm_cxl_add_memdev(cxlds);
if (IS_ERR(cxlmd))
return PTR_ERR(cxlmd);
--
2.37.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
` (2 preceding siblings ...)
2023-03-24 17:13 ` [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
@ 2023-03-24 17:13 ` Jonathan Cameron
2023-03-24 21:12 ` kernel test robot
` (4 more replies)
2023-03-24 17:13 ` [PATCH v2 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
4 siblings, 5 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
CXL rev 3.0 introduces a standard performance monitoring hardware
block to CXL. Instances are discovered using CXL Register Locator DVSEC
entries. Each CXL component may have multiple PMUs.
This initial driver supports on a subset of types of counter.
It support counters that are either fixed or configurable, but requires
that they support the ability to freeze and write value whilst frozen.
Development done with QEMU model which will be posted shortly.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Thanks to Kan Liang for detailed review and discussion of the configurability
description to userspace. Note that complexity is left for a future patch set.
v2:
- Split the events list in to configurable and fixed cases.
- Add utility functions to search each list.
- Allow fallback to configurable counter if fixed counter for same
thing is already in use.
- Fix check of filter.
- Add a macro for the CXL defined events and use the
PCI_DVSEC_VENDOR_ID_CXL define. Sure this isn't DVSEC but the
value was first used there and naming that define is complex for
fun legal reasons.
- Verify the event capability for what is requested is possible
in cpmu_event_init() to error out earlier if not.
- Drop an unnecessary check on enable in cpmu_pmu_enable()
- Use bitmap manipulation to make it cheaper to find an unused counter.
---
drivers/cxl/Kconfig | 12 +
drivers/cxl/Makefile | 1 +
drivers/cxl/cpmu.c | 937 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 950 insertions(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index ff4e78117b31..d68fc5769c58 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -139,4 +139,16 @@ config CXL_REGION_INVALIDATION_TEST
If unsure, or if this kernel is meant for production environments,
say N.
+config CXL_CPMU
+ tristate "CXL Performance Monitoring Unit"
+ default CXL_BUS
+ help
+ Support performance monitoring as defined in CXL rev 3.0
+ section 13.2: Performance Monitoring. CXL components may have
+ one or more CXL Performance Monitoring Units (CPMUs).
+
+ Say 'y/m' to enable a driver that will attach to performance
+ monitoring units and provide standard perf based interfaces.
+
+ If unsure say 'm'.
endif
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index db321f48ba52..024bb739554b 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_CXL_MEM) += cxl_mem.o
obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
obj-$(CONFIG_CXL_PORT) += cxl_port.o
+obj-$(CONFIG_CXL_CPMU) += cpmu.o
cxl_mem-y := mem.o
cxl_pci-y := pci.o
diff --git a/drivers/cxl/cpmu.c b/drivers/cxl/cpmu.c
new file mode 100644
index 000000000000..7a259f9de05e
--- /dev/null
+++ b/drivers/cxl/cpmu.c
@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright(c) 2023 Huawei
+ *
+ * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
+ * called the CXL PMU, or CPMU. In order to allow a high degree of
+ * implementation flexibility the specification provides a wide range of
+ * options all of which are self describing.
+ *
+ * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
+ *
+ * TODO
+ * o Discoverability of counters. Allow perftool to provide summed counters
+ * and vendor defined counters.
+ * o Support free running counters - copy the Intel uncore PMU handling for these.
+ * o CPMUs which do not support freeze.
+ * o Add filter validation in cpmu_event_init() so problems are detected earlier.
+ * o Reject configurations that the hardware is ignoring
+ * (e.g. invert when not invertible)
+ * o Support CPMUs with no interrupts using an HRTIMER.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bits.h>
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/perf_event.h>
+#include "cpmu.h"
+#include "cxlpci.h"
+#include "cxl.h"
+
+/* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
+#define CPMU_GID_CLOCK_TICKS 0x00
+#define CPMU_GID_D2H_REQ 0x0010
+#define CPMU_GID_D2H_RSP 0x0011
+#define CPMU_GID_H2D_REQ 0x0012
+#define CPMU_GID_H2D_RSP 0x0013
+#define CPMU_GID_CACHE_DATA 0x0014
+#define CPMU_GID_M2S_REQ 0x0020
+#define CPMU_GID_M2S_RWD 0x0021
+#define CPMU_GID_M2S_BIRSP 0x0022
+#define CPMU_GID_S2M_BISNP 0x0023
+#define CPMU_GID_S2M_NDR 0x0024
+#define CPMU_GID_S2M_DRS 0x0025
+#define CPMU_GID_DDR 0x8000
+
+static int cpmu_cpuhp_state_num;
+
+struct cpmu_event {
+ u16 vid;
+ u16 gid;
+ u32 msk;
+ union {
+ int counter_idx; /* fixed counters */
+ int event_idx; /* configurable counters */
+ };
+ struct list_head node;
+};
+
+#define CPMU_MAX_COUNTERS 64
+struct cpmu_info {
+ struct pmu pmu;
+ void __iomem *base;
+ struct perf_event **hw_events;
+ struct list_head events_configurable;
+ struct list_head events_fixed;
+ DECLARE_BITMAP(used_counter_bm, CPMU_MAX_COUNTERS);
+ DECLARE_BITMAP(conf_counter_bm, CPMU_MAX_COUNTERS);
+ u16 counter_width;
+ u8 num_counters;
+ u8 num_event_capabilities;
+ int on_cpu;
+ struct hlist_node node;
+ bool freeze_for_enable;
+ bool filter_hdm;
+ int irq;
+};
+
+#define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
+
+/*
+ * All CPMU counters are discoverable via the Event Capabilities Registers.
+ * Each Event Capability register contains a a VID / GroupID.
+ * A counter may then count any combination (by summing) of events in
+ * that group which are in the Supported Events Bitmask.
+ * However, there are some complexities to the scheme.
+ * - Fixed function counters refer to an Event Capabilities register.
+ * That event capability register is not then used for Configurable
+ * counters.
+ */
+static int cpmu_parse_caps(struct device *dev, struct cpmu_info *info)
+{
+ DECLARE_BITMAP(fixed_counter_event_cap_bm, 32) = {0};
+ void __iomem *base = info->base;
+ u64 val, eval;
+ int i;
+
+ val = readq(base + CPMU_CAP_REG);
+ info->freeze_for_enable = FIELD_GET(CPMU_CAP_WRITEABLE_WHEN_FROZEN, val) &
+ FIELD_GET(CPMU_CAP_FREEZE, val);
+ if (!info->freeze_for_enable) {
+ dev_err(dev, "Driver does not support CPMUs that do not support freeze for enable\n");
+ return -ENODEV;
+ }
+
+ info->num_counters = FIELD_GET(CPMU_CAP_NUM_COUNTERS_MSK, val) + 1;
+ info->counter_width = FIELD_GET(CPMU_CAP_COUNTER_WIDTH_MSK, val);
+ info->num_event_capabilities = FIELD_GET(CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;
+
+ info->filter_hdm = FIELD_GET(CPMU_CAP_FILTERS_SUP_MSK, val) & CPMU_FILTER_HDM;
+ if (FIELD_GET(CPMU_CAP_INT, val))
+ info->irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
+ else
+ info->irq = -1;
+
+ /* First handle fixed function counters; note if configurable counters found */
+ for (i = 0; i < info->num_counters; i++) {
+ struct cpmu_event *cpmu_ev;
+ u32 events_msk;
+ u8 group_idx;
+
+ val = readq(base + CPMU_COUNTER_CFG_REG(i));
+
+ if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) ==
+ CPMU_COUNTER_CFG_TYPE_CONFIGURABLE) {
+ set_bit(i, info->conf_counter_bm);
+ }
+
+ if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) !=
+ CPMU_COUNTER_CFG_TYPE_FIXED_FUN)
+ continue;
+
+ /* In this case we know which fields are const */
+ group_idx = FIELD_GET(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);
+ events_msk = FIELD_GET(CPMU_COUNTER_CFG_EVENTS_MSK, val);
+ eval = readq(base + CPMU_EVENT_CAP_REG(group_idx));
+ cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
+ if (!cpmu_ev)
+ return -ENOMEM;
+
+ cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
+ cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
+ /* For a fixed purpose counter use the events mask from the counter CFG */
+ cpmu_ev->msk = events_msk;
+ cpmu_ev->counter_idx = i;
+ /* This list add is never unwound as all entries deleted on remove */
+ list_add(&cpmu_ev->node, &info->events_fixed);
+ /*
+ * Configurable counters must not use an Event Capability registers that
+ * is in use for a Fixed counter
+ */
+ set_bit(group_idx, fixed_counter_event_cap_bm);
+ }
+
+ if (!bitmap_empty(info->conf_counter_bm, CPMU_MAX_COUNTERS)) {
+ struct cpmu_event *cpmu_ev;
+ int j;
+ /* Walk event capabilities unused by fixed counters */
+ for_each_clear_bit(j, fixed_counter_event_cap_bm,
+ info->num_event_capabilities) {
+ cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
+ if (!cpmu_ev)
+ return -ENOMEM;
+
+ eval = readq(base + CPMU_EVENT_CAP_REG(j));
+ cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
+ cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
+ cpmu_ev->msk = FIELD_GET(CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);
+ cpmu_ev->event_idx = j;
+ list_add(&cpmu_ev->node, &info->events_configurable);
+ }
+ }
+
+ return 0;
+}
+
+static ssize_t cpmu_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ return sysfs_emit(buf, "config=%#llx\n", pmu_attr->id);
+}
+
+#define CPMU_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
+ PMU_EVENT_ATTR_ID(_name, cpmu_event_sysfs_show, \
+ ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
+
+/* For CXL spec defined events */
+#define CPMU_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
+ CPMU_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
+
+static struct attribute *cpmu_event_attrs[] = {
+ CPMU_PMU_EVENT_CXL_ATTR(clock_ticks, CPMU_GID_CLOCK_TICKS, BIT(0)),
+ /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdcurr, CPMU_GID_D2H_REQ, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdown, CPMU_GID_D2H_REQ, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdshared, CPMU_GID_D2H_REQ, BIT(3)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdany, CPMU_GID_D2H_REQ, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdownnodata, CPMU_GID_D2H_REQ, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_itomwr, CPMU_GID_D2H_REQ, BIT(6)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wrcurr, CPMU_GID_D2H_REQ, BIT(7)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_clflush, CPMU_GID_D2H_REQ, BIT(8)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cleanevict, CPMU_GID_D2H_REQ, BIT(9)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_dirtyevict, CPMU_GID_D2H_REQ, BIT(10)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cleanevictnodata, CPMU_GID_D2H_REQ, BIT(11)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wowrinv, CPMU_GID_D2H_REQ, BIT(12)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wowrinvf, CPMU_GID_D2H_REQ, BIT(13)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wrinv, CPMU_GID_D2H_REQ, BIT(14)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cacheflushed, CPMU_GID_D2H_REQ, BIT(16)),
+ /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspihiti, CPMU_GID_D2H_RSP, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspvhitv, CPMU_GID_D2H_RSP, BIT(6)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspihitse, CPMU_GID_D2H_RSP, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspshitse, CPMU_GID_D2H_RSP, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspsfwdm, CPMU_GID_D2H_RSP, BIT(7)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspifwdm, CPMU_GID_D2H_RSP, BIT(15)),
+ CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspvfwdv, CPMU_GID_D2H_RSP, BIT(22)),
+ /* CXL rev 3.0 Table 3-21 - CXL.cache - Mapping of H2D Requests to D2H Responses */
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpdata, CPMU_GID_H2D_REQ, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpinv, CPMU_GID_H2D_REQ, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpcur, CPMU_GID_H2D_REQ, BIT(3)),
+ /* CXL rev 3.0 Table 3-22 - H2D Response Opcode Encodings */
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_writepull, CPMU_GID_H2D_RSP, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_go, CPMU_GID_H2D_RSP, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_gowritepull, CPMU_GID_H2D_RSP, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_extcmp, CPMU_GID_H2D_RSP, BIT(6)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_gowritepulldrop, CPMU_GID_H2D_RSP, BIT(8)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_fastgowritepull, CPMU_GID_H2D_RSP, BIT(13)),
+ CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_goerrwritepull, CPMU_GID_H2D_RSP, BIT(15)),
+ /* CXL rev 3.0 Table 13-5 directly lists these */
+ CPMU_PMU_EVENT_CXL_ATTR(cachedata_d2h_data, CPMU_GID_CACHE_DATA, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(cachedata_h2d_data, CPMU_GID_CACHE_DATA, BIT(1)),
+ /* CXL rev 3.0 Table 3-29 M2S Req Memory Opcodes */
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_meminv, CPMU_GID_M2S_REQ, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrd, CPMU_GID_M2S_REQ, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrddata, CPMU_GID_M2S_REQ, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrdfwd, CPMU_GID_M2S_REQ, BIT(3)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memwrfwd, CPMU_GID_M2S_REQ, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memspecrd, CPMU_GID_M2S_REQ, BIT(8)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_meminvnt, CPMU_GID_M2S_REQ, BIT(9)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memcleanevict, CPMU_GID_M2S_REQ, BIT(10)),
+ /* CXL rev 3.0 Table 3-35 M2S RwD Memory Opcodes */
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_memwr, CPMU_GID_M2S_RWD, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_memwrptl, CPMU_GID_M2S_RWD, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_biconflict, CPMU_GID_M2S_RWD, BIT(4)),
+ /* CXL rev 3.0 Table 3-38 M2S BIRsp Memory Opcodes */
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_i, CPMU_GID_M2S_BIRSP, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_s, CPMU_GID_M2S_BIRSP, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_e, CPMU_GID_M2S_BIRSP, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_iblk, CPMU_GID_M2S_BIRSP, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_sblk, CPMU_GID_M2S_BIRSP, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_eblk, CPMU_GID_M2S_BIRSP, BIT(6)),
+ /* CXL rev 3.0 Table 3-40 S2M BISnp Opcodes */
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_cur, CPMU_GID_S2M_BISNP, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_data, CPMU_GID_S2M_BISNP, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_inv, CPMU_GID_S2M_BISNP, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk, CPMU_GID_S2M_BISNP, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk, CPMU_GID_S2M_BISNP, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk, CPMU_GID_S2M_BISNP, BIT(6)),
+ /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CPMU_GID_S2M_NDR, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CPMU_GID_S2M_NDR, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CPMU_GID_S2M_NDR, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CPMU_GID_S2M_NDR, BIT(3)),
+ /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CPMU_GID_S2M_DRS, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CPMU_GID_S2M_DRS, BIT(1)),
+ /* CXL rev 3.0 Table 13-5 directly lists these */
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_act, CPMU_GID_DDR, BIT(0)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_pre, CPMU_GID_DDR, BIT(1)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_casrd, CPMU_GID_DDR, BIT(2)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_caswr, CPMU_GID_DDR, BIT(3)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_refresh, CPMU_GID_DDR, BIT(4)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_selfrefreshent, CPMU_GID_DDR, BIT(5)),
+ CPMU_PMU_EVENT_CXL_ATTR(ddr_rfm, CPMU_GID_DDR, BIT(6)),
+ NULL
+};
+
+static struct cpmu_event *cpmu_find_fixed_counter_event(struct cpmu_info *info,
+ int vid, int gid, int msk)
+{
+ struct cpmu_event *cpmu_ev;
+
+ list_for_each_entry(cpmu_ev, &info->events_fixed, node) {
+ if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
+ continue;
+
+ /* Precise match for fixed counter */
+ if (msk == cpmu_ev->msk)
+ return cpmu_ev;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
+static struct cpmu_event *cpmu_find_config_counter_event(struct cpmu_info *info,
+ int vid, int gid, int msk)
+{
+ struct cpmu_event *cpmu_ev;
+
+ list_for_each_entry(cpmu_ev, &info->events_configurable, node) {
+ if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
+ continue;
+
+ /* Request mask must be subset of supported */
+ if (msk & ~cpmu_ev->msk)
+ continue;
+
+ return cpmu_ev;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
+static umode_t cpmu_event_is_visible(struct kobject *kobj, struct attribute *attr, int a)
+{
+ struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr);
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(dev_attr, struct perf_pmu_events_attr, attr);
+ struct device *dev = kobj_to_dev(kobj);
+ struct cpmu_info *info = dev_get_drvdata(dev);
+ int vid = FIELD_GET(GENMASK_ULL(63, 48), pmu_attr->id);
+ int gid = FIELD_GET(GENMASK_ULL(47, 32), pmu_attr->id);
+ int msk = FIELD_GET(GENMASK_ULL(31, 0), pmu_attr->id);
+
+ if (!IS_ERR(cpmu_find_fixed_counter_event(info, vid, gid, msk)))
+ return attr->mode;
+
+ if (!IS_ERR(cpmu_find_config_counter_event(info, vid, gid, msk)))
+ return attr->mode;
+
+ return 0;
+}
+
+static const struct attribute_group cpmu_events = {
+ .name = "events",
+ .attrs = cpmu_event_attrs,
+ .is_visible = cpmu_event_is_visible,
+};
+
+static ssize_t cpmu_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sysfs_emit(buf, "%s\n", (char *)eattr->var);
+}
+
+#define CPMU_FORMAT_ATTR(_name, _format)\
+ (&((struct dev_ext_attribute[]) { \
+ { \
+ .attr = __ATTR(_name, 0444, \
+ cpmu_format_sysfs_show, NULL), \
+ .var = (void *)_format \
+ } \
+ })[0].attr.attr)
+
+enum {
+ cpmu_mask_attr,
+ cpmu_gid_attr,
+ cpmu_vid_attr,
+ cpmu_threshold_attr,
+ cpmu_invert_attr,
+ cpmu_edge_attr,
+ cpmu_hdm_filter_en_attr,
+ cpmu_hdm_attr,
+};
+
+static struct attribute *cpmu_format_attr[] = {
+ [cpmu_mask_attr] = CPMU_FORMAT_ATTR(mask, "config:0-31"),
+ [cpmu_gid_attr] = CPMU_FORMAT_ATTR(gid, "config:32-47"),
+ [cpmu_vid_attr] = CPMU_FORMAT_ATTR(vid, "config:48-63"),
+ [cpmu_threshold_attr] = CPMU_FORMAT_ATTR(threshold, "config1:0-15"),
+ [cpmu_invert_attr] = CPMU_FORMAT_ATTR(invert, "config1:16"),
+ [cpmu_edge_attr] = CPMU_FORMAT_ATTR(edge, "config1:17"),
+ [cpmu_hdm_filter_en_attr] = CPMU_FORMAT_ATTR(hdm_filter_en, "config1:18"),
+ [cpmu_hdm_attr] = CPMU_FORMAT_ATTR(hdm, "config2:0-15"),
+ NULL
+};
+
+static umode_t cpmu_format_is_visible(struct kobject *kobj, struct attribute *attr, int a)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ /*
+ * Filter capability at the CPMU level, so hide the attributes if the particular
+ * filter is not supported.
+ */
+ if (attr == cpmu_format_attr[cpmu_hdm_filter_en_attr] ||
+ attr == cpmu_format_attr[cpmu_hdm_attr]) {
+ if (info->filter_hdm)
+ return 0444;
+ else
+ return 0;
+ } else {
+ return 0444;
+ }
+}
+
+static const struct attribute_group cpmu_format_group = {
+ .name = "format",
+ .attrs = cpmu_format_attr,
+ .is_visible = cpmu_format_is_visible,
+};
+
+static u32 cpmu_config_get_mask(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
+}
+
+static u16 cpmu_config_get_gid(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
+}
+
+static u16 cpmu_config_get_vid(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
+}
+
+static u8 cpmu_config1_get_threshold(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK_ULL(15, 0), event->attr.config1);
+}
+
+static bool cpmu_config1_get_invert(struct perf_event *event)
+{
+ return FIELD_GET(BIT(16), event->attr.config1);
+}
+
+static bool cpmu_config1_get_edge(struct perf_event *event)
+{
+ return FIELD_GET(BIT(17), event->attr.config1);
+}
+
+/*
+ * CPMU specification allows for 8 filters, each with a 16 bit value...
+ * So we need to find 8x16bits to store it in.
+ * As the value used for disable is 0xffff, a separate enable switch
+ * is needed.
+ */
+
+static bool cpmu_config1_hdm_filter_en(struct perf_event *event)
+{
+ return FIELD_GET(BIT(14), event->attr.config1);
+}
+
+static u16 cpmu_config2_get_hdm_decoder(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(15, 0), event->attr.config2);
+}
+
+static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ return cpumap_print_to_pagebuf(true, buf, cpumask_of(info->on_cpu));
+}
+static DEVICE_ATTR_RO(cpumask);
+
+static struct attribute *cpmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL
+};
+
+static const struct attribute_group cpmu_cpumask_group = {
+ .attrs = cpmu_cpumask_attrs,
+};
+
+static const struct attribute_group *cpmu_attr_groups[] = {
+ &cpmu_events,
+ &cpmu_format_group,
+ &cpmu_cpumask_group,
+ NULL
+};
+
+/* If counter_idx == NULL, don't try to allocate a counter. */
+static int cpmu_get_event_idx(struct perf_event *event, int *counter_idx, int *event_idx)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ DECLARE_BITMAP(configurable_and_free, CPMU_MAX_COUNTERS);
+ struct cpmu_event *cpmu_ev;
+ u32 mask;
+ u16 gid, vid;
+ int i;
+
+ vid = cpmu_config_get_vid(event);
+ gid = cpmu_config_get_gid(event);
+ mask = cpmu_config_get_mask(event);
+
+ cpmu_ev = cpmu_find_fixed_counter_event(info, vid, gid, mask);
+ if (!IS_ERR(cpmu_ev)) {
+ if (!counter_idx)
+ return 0;
+ if (!info->hw_events[cpmu_ev->counter_idx]) {
+ *counter_idx = cpmu_ev->counter_idx;
+ return 0;
+ }
+ /* Fixed counter is in use, but maybe a configurable one? */
+ }
+
+ cpmu_ev = cpmu_find_config_counter_event(info, vid, gid, mask);
+ if (!IS_ERR(cpmu_ev)) {
+ if (!counter_idx)
+ return 0;
+
+ bitmap_andnot(configurable_and_free, info->conf_counter_bm,
+ info->used_counter_bm, CPMU_MAX_COUNTERS);
+
+ i = find_first_bit(configurable_and_free, CPMU_MAX_COUNTERS);
+ if (i == CPMU_MAX_COUNTERS)
+ return -EINVAL;
+
+ *counter_idx = i;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int cpmu_event_init(struct perf_event *event)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+
+ event->cpu = info->on_cpu;
+ /* Top level type sanity check - is this a Hardware Event being requested */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+ return -EOPNOTSUPP;
+ /* TODO: Validation of any filter */
+
+ /*
+ * Verify that it is possible to count what was requested. Either must
+ * be a fixed counter that is a precise match or a configurable counter
+ * where this is a subset.
+ */
+ return cpmu_get_event_idx(event, NULL, NULL);
+}
+
+static void cpmu_pmu_enable(struct pmu *pmu)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(pmu);
+ void __iomem *base = info->base;
+
+ /* We don't have a global enable, but we 'might' have a global freeze which we can use */
+ if (info->freeze_for_enable) {
+ /* Can assume frozen at this stage */
+ writeq(0, base + CPMU_FREEZE_REG);
+
+ return;
+ }
+}
+
+static void cpmu_pmu_disable(struct pmu *pmu)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(pmu);
+ void __iomem *base = info->base;
+
+ if (info->freeze_for_enable) {
+ /*
+ * Whilst bits above number of counters are RsvdZ
+ * they are unlikely to be repurposed given
+ * number of counters is allowed to be 64 leaving
+ * no reserved bits. Hence this is only slightly
+ * naughty.
+ */
+ writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
+ return;
+ }
+}
+
+static void cpmu_event_start(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ void __iomem *base = info->base;
+ u64 cfg, prev_cnt;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ /*
+ * Currently only hdm filter control is implemnted, this code will
+ * want generalizing when more filters are added.
+ */
+ if (info->filter_hdm) {
+ if (cpmu_config1_hdm_filter_en(event))
+ cfg = cpmu_config2_get_hdm_decoder(event);
+ else
+ cfg = GENMASK(15, 0);
+ writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
+ }
+
+ cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
+
+ /* Fixed purpose counters have next two fields RO */
+ if (test_bit(hwc->idx, info->conf_counter_bm)) {
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
+ }
+ cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
+ /*
+ * For events that generate only 1 count per clock the CXL 3.0 spec
+ * states the threshold shall be set to 1 but if set to 0 it will
+ * count the raw value anwyay?
+ * There is no definition of what events will count multiple per cycle
+ * and hence to which non 1 values of threshold can apply.
+ * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
+ */
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
+ cpmu_config1_get_threshold(event));
+ writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
+
+ local64_set(&hwc->prev_count, 0);
+ writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
+
+ if (flags & PERF_EF_RELOAD) {
+ prev_cnt = local64_read(&hwc->prev_count);
+ writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
+ }
+
+ perf_event_update_userpage(event);
+}
+
+static u64 cpmu_read_counter(struct perf_event *event)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ void __iomem *base = info->base;
+
+ return readq(base + CPMU_COUNTER_REG(event->hw.idx));
+}
+
+static void __cpmu_read(struct perf_event *event, bool overflow)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ u64 new_cnt, prev_cnt, delta;
+
+ do {
+ prev_cnt = local64_read(&hwc->prev_count);
+ new_cnt = cpmu_read_counter(event);
+ } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
+
+ /*
+ * If we know an overflow occur then take that into account.
+ * Note counter is not reset as that would lose events
+ */
+ delta = (new_cnt - prev_cnt) & GENMASK(info->counter_width - 1, 0);
+ if (overflow && delta < GENMASK(info->counter_width - 1, 0))
+ delta += (1UL << info->counter_width);
+
+ local64_add(delta, &event->count);
+}
+
+static void cpmu_read(struct perf_event *event)
+{
+ __cpmu_read(event, false);
+}
+
+static void cpmu_event_stop(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ void __iomem *base = info->base;
+ struct hw_perf_event *hwc = &event->hw;
+ u64 cfg;
+
+ cpmu_read(event);
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
+ cfg &= ~(FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1) |
+ FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1));
+ writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+/*
+ * Reset ensures no possibility of any information leaking to wrong
+ * counter. Note that all fields written during start()
+ */
+static void cpmu_reset_counter(struct cpmu_info *info, int idx)
+{
+ void __iomem *base = info->base;
+
+ /* Much of this register is read only */
+ writeq(0, base + CPMU_EVENT_CAP_REG(idx));
+ /* Filters are not per counter, so no reset here */
+ writeq(0, base + CPMU_COUNTER_REG(idx));
+}
+
+static int cpmu_event_add(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx, rc;
+ int event_idx = 0;
+
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+
+ rc = cpmu_get_event_idx(event, &idx, &event_idx);
+ if (rc < 0)
+ return rc;
+
+ hwc->idx = idx;
+
+ /* Only set for configurable counters */
+ hwc->event_base = event_idx;
+ info->hw_events[idx] = event;
+ set_bit(idx, info->used_counter_bm);
+
+ cpmu_reset_counter(info, idx);
+
+ if (flags & PERF_EF_START)
+ cpmu_event_start(event, PERF_EF_RELOAD);
+
+ return 0;
+}
+
+static void cpmu_event_del(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ cpmu_event_stop(event, PERF_EF_UPDATE);
+ clear_bit(hwc->idx, info->used_counter_bm);
+ info->hw_events[hwc->idx] = NULL;
+ perf_event_update_userpage(event);
+}
+
+static irqreturn_t cpmu_irq(int irq, void *data)
+{
+ struct cpmu_info *info = data;
+ void __iomem *base = info->base;
+ u64 overflowed;
+ DECLARE_BITMAP(overflowedbm, 64);
+ int i;
+
+ overflowed = readq(base + CPMU_OVERFLOW_REG);
+
+ /* Interrupt may be shared, so maybe it isn't ours */
+ if (!overflowed)
+ return IRQ_NONE;
+
+ bitmap_from_arr64(overflowedbm, &overflowed, 64);
+ for_each_set_bit(i, overflowedbm, info->num_counters) {
+ struct perf_event *event = info->hw_events[i];
+
+ if (!event) {
+ dev_dbg(info->pmu.dev,
+ "overflow but on non enabled counter %d\n", i);
+ continue;
+ }
+
+ __cpmu_read(event, true);
+ }
+
+ writeq(overflowed, base + CPMU_OVERFLOW_REG);
+
+ return IRQ_HANDLED;
+}
+
+static int cxl_cpmu_probe(struct device *dev)
+{
+ struct cxl_cpmu *cpmu = to_cxl_cpmu(dev);
+ struct pci_dev *pdev = to_pci_dev(dev->parent);
+ struct cpmu_info *info;
+ char *irq_name;
+ int rc, irq;
+
+ info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&info->events_fixed);
+ INIT_LIST_HEAD(&info->events_configurable);
+
+ info->base = cpmu->base;
+
+ info->on_cpu = -1;
+ rc = cpmu_parse_caps(dev, info);
+ if (rc)
+ return rc;
+
+ info->hw_events = devm_kcalloc(dev, sizeof(*info->hw_events),
+ info->num_counters, GFP_KERNEL);
+ if (!info->hw_events)
+ return -ENOMEM;
+
+ info->pmu = (struct pmu) {
+ .name = dev_name(dev),
+ .parent = dev,
+ .module = THIS_MODULE,
+ .event_init = cpmu_event_init,
+ .pmu_enable = cpmu_pmu_enable,
+ .pmu_disable = cpmu_pmu_disable,
+ .add = cpmu_event_add,
+ .del = cpmu_event_del,
+ .start = cpmu_event_start,
+ .stop = cpmu_event_stop,
+ .read = cpmu_read,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = cpmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ };
+
+ if (info->irq <= 0)
+ return -EINVAL;
+
+ rc = pci_irq_vector(pdev, info->irq);
+ if (rc < 0)
+ return rc;
+ irq = rc;
+
+ irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_overflow\n", dev_name(dev));
+ if (!irq_name)
+ return -ENOMEM;
+
+ rc = devm_request_irq(dev, irq, cpmu_irq, IRQF_SHARED, irq_name, info);
+ if (rc)
+ return rc;
+ info->irq = irq;
+
+ rc = cpuhp_state_add_instance(cpmu_cpuhp_state_num, &info->node);
+ if (rc)
+ return rc;
+
+ rc = perf_pmu_register(&info->pmu, info->pmu.name, -1);
+ if (rc)
+ return rc;
+
+ dev_set_drvdata(dev, info);
+
+ return 0;
+}
+
+static void cxl_cpmu_remove(struct device *dev)
+{
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ perf_pmu_unregister(&info->pmu);
+ cpuhp_state_remove_instance_nocalls(cpmu_cpuhp_state_num, &info->node);
+}
+
+static struct cxl_driver cxl_cpmu_driver = {
+ .name = "cxl_cpmu",
+ .probe = cxl_cpmu_probe,
+ .remove = cxl_cpmu_remove,
+ .id = CXL_DEVICE_CPMU,
+};
+
+static int cpmu_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
+
+ if (info->on_cpu != -1)
+ return 0;
+
+ info->on_cpu = cpu;
+ WARN_ON(irq_set_affinity(info->irq, cpumask_of(cpu)));
+
+ return 0;
+}
+
+static int cpmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
+ unsigned int target;
+
+ if (info->on_cpu != cpu)
+ return 0;
+
+ info->on_cpu = -1;
+ target = cpumask_first(cpu_online_mask);
+ if (target >= nr_cpu_ids) {
+ dev_err(info->pmu.dev, "Unable to find a suitable CPU\n");
+ return 0;
+ }
+
+ perf_pmu_migrate_context(&info->pmu, cpu, target);
+ info->on_cpu = target;
+ WARN_ON(irq_set_affinity(info->irq, cpumask_of(target)));
+
+ return 0;
+}
+
+static __init int cxl_cpmu_init(void)
+{
+ int rc;
+
+ rc = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
+ "AP_PERF_CPMU_ONLINE",
+ cpmu_online_cpu, cpmu_offline_cpu);
+ if (rc < 0)
+ return rc;
+ cpmu_cpuhp_state_num = rc;
+
+ rc = cxl_driver_register(&cxl_cpmu_driver);
+ if (rc)
+ cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
+
+ return rc;
+}
+
+static __exit void cxl_cpmu_exit(void)
+{
+ cxl_driver_unregister(&cxl_cpmu_driver);
+ cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(CXL);
+module_init(cxl_cpmu_init);
+module_exit(cxl_cpmu_exit);
+MODULE_ALIAS_CXL(CXL_DEVICE_CPMU);
--
2.37.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver.
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
` (3 preceding siblings ...)
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
@ 2023-03-24 17:13 ` Jonathan Cameron
4 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-24 17:13 UTC (permalink / raw)
To: Liang Kan, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
Very basic introduction to the device and the current driver support
provided. I expect to expand on this in future versions of this patch
set.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
--
v2:
- Not renamed the device as now an earlier patch allows the pmu->device
to have a parent thus making the association explicit.
v1:
- Add docs for how to use a Vendor Defined Counter.
---
Documentation/admin-guide/perf/cxl.rst | 65 ++++++++++++++++++++++++
Documentation/admin-guide/perf/index.rst | 1 +
2 files changed, 66 insertions(+)
diff --git a/Documentation/admin-guide/perf/cxl.rst b/Documentation/admin-guide/perf/cxl.rst
new file mode 100644
index 000000000000..46235dff4b21
--- /dev/null
+++ b/Documentation/admin-guide/perf/cxl.rst
@@ -0,0 +1,65 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================================
+CXL Performance Monitoring Unit (CPMU)
+======================================
+
+The CXL rev 3.0 specification provides a definition of CXL Performance
+Monitoring Unit in section 13.2: Performance Monitoring.
+
+CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
+any number of CPMU instances. CPMU capabilities are fully discoverable from
+the devices. The specification provides event definitions for all CXL protocol
+message types and a set of additional events for things commonly counted on
+CXL devices (e.g. DRAM events).
+
+CPMU driver
+===========
+
+The CPMU driver register a perf PMU with the name cpmu<id> on the CXL bus.
+
+ /sys/bus/cxl/device/cpmu<id>
+
+The associated PMU is registered as
+
+ /sys/bus/event_sources/devices/cpmu<id>
+
+In common with other CXL bus devices, the id has no specific meaning and the
+relationship to specific CXL device should be established via the device parent
+of the device on the CXL bus.
+
+PMU driver provides description of available events and filter options in sysfs.
+
+The "format" directory describes all formats of the config (event vendor id,
+group id and mask) config1 (threshold, filter enables) and config2 (filter
+parameters) fields of the perf_event_attr structure. The "events" directory
+describes all documented events show in perf list.
+
+The events shown in perf list are the most fine grained events with a single
+bit of the event mask set. More general events may be enable by setting
+multiple mask bits in config. For example, all Device to Host Read Requests
+may be captured on a single counter by setting the bits for all of
+
+* d2h_req_rdcurr
+* d2h_req_rdown
+* d2h_req_rdshared
+* d2h_req_rdany
+* d2h_req_rdownnodata
+
+Example of usage::
+
+ $#perf list
+ cpmu0/clock_ticks/ [Kernel PMU event]
+ cpmu0/d2h_req_itomwr/ [Kernel PMU event]
+ cpmu0/d2h_req_rdany/ [Kernel PMU event]
+ cpmu0/d2h_req_rdcurr/ [Kernel PMU event]
+ -----------------------------------------------------------
+
+ $# perf stat -e cpmu0/clock_ticks/ -e cpmu0/d2h_req_itowrm/
+
+Vendor specific events may also be available and if so can be used via
+
+ $# perf stat -e cpmu0/vid=VID,gid=GID,mask=MASK/
+
+The driver does not support sampling. So "perf record" and attaching to
+a task are unsupported.
diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst
index 9de64a40adab..f60be04e4e33 100644
--- a/Documentation/admin-guide/perf/index.rst
+++ b/Documentation/admin-guide/perf/index.rst
@@ -21,3 +21,4 @@ Performance monitor support
alibaba_pmu
nvidia-pmu
meson-ddr-pmu
+ cxl
--
2.37.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices
2023-03-24 17:13 ` [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
@ 2023-03-24 21:01 ` kernel test robot
2023-03-27 15:50 ` Jonathan Cameron
0 siblings, 1 reply; 20+ messages in thread
From: kernel test robot @ 2023-03-24 21:01 UTC (permalink / raw)
To: Jonathan Cameron, Liang Kan, linux-cxl, peterz
Cc: llvm, oe-kbuild-all, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
Hi Jonathan,
I love your patch! Yet something to improve:
[auto build test ERROR on acme/perf/core]
[also build test ERROR on tip/perf/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
patch link: https://lore.kernel.org/r/20230324171313.18448-4-Jonathan.Cameron%40huawei.com
patch subject: [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices
config: arm-randconfig-r023-20230322 (https://download.01.org/0day-ci/archive/20230325/202303250419.FANh4fIC-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 67409911353323ca5edf2049ef0df54132fa1ca7)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/intel-lab-lkp/linux/commit/ab99ab31e5c4aa9f68425f3505f22a790d64bfe9
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
git checkout ab99ab31e5c4aa9f68425f3505f22a790d64bfe9
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303250419.FANh4fIC-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/cxl/core/port.c:60:20: error: use of undeclared identifier 'cxl_cpmu_type'; did you mean 'cxl_bus_type'?
if (dev->type == &cxl_cpmu_type)
^~~~~~~~~~~~~
cxl_bus_type
drivers/cxl/cxl.h:732:24: note: 'cxl_bus_type' declared here
extern struct bus_type cxl_bus_type;
^
1 error generated.
vim +60 drivers/cxl/core/port.c
40
41 static int cxl_device_id(const struct device *dev)
42 {
43 if (dev->type == &cxl_nvdimm_bridge_type)
44 return CXL_DEVICE_NVDIMM_BRIDGE;
45 if (dev->type == &cxl_nvdimm_type)
46 return CXL_DEVICE_NVDIMM;
47 if (dev->type == CXL_PMEM_REGION_TYPE())
48 return CXL_DEVICE_PMEM_REGION;
49 if (dev->type == CXL_DAX_REGION_TYPE())
50 return CXL_DEVICE_DAX_REGION;
51 if (is_cxl_port(dev)) {
52 if (is_cxl_root(to_cxl_port(dev)))
53 return CXL_DEVICE_ROOT;
54 return CXL_DEVICE_PORT;
55 }
56 if (is_cxl_memdev(dev))
57 return CXL_DEVICE_MEMORY_EXPANDER;
58 if (dev->type == CXL_REGION_TYPE())
59 return CXL_DEVICE_REGION;
> 60 if (dev->type == &cxl_cpmu_type)
61 return CXL_DEVICE_CPMU;
62 return 0;
63 }
64
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
@ 2023-03-24 21:12 ` kernel test robot
2023-03-27 15:50 ` Jonathan Cameron
2023-03-24 21:42 ` kernel test robot
` (3 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: kernel test robot @ 2023-03-24 21:12 UTC (permalink / raw)
To: Jonathan Cameron, Liang Kan, linux-cxl, peterz
Cc: oe-kbuild-all, mingo, acme, mark.rutland, will, dan.j.williams,
linuxarm, linux-perf-users, linux-kernel, Davidlohr Bueso,
Dave Jiang
Hi Jonathan,
I love your patch! Yet something to improve:
[auto build test ERROR on acme/perf/core]
[also build test ERROR on tip/perf/core cxl/next cxl/pending linus/master v6.3-rc3 next-20230324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
patch link: https://lore.kernel.org/r/20230324171313.18448-5-Jonathan.Cameron%40huawei.com
patch subject: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
config: parisc-randconfig-r036-20230324 (https://download.01.org/0day-ci/archive/20230325/202303250523.JdddC4Ld-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
git checkout a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=parisc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=parisc SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303250523.JdddC4Ld-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/cxl/cpmu.c: In function 'cpmu_parse_caps':
drivers/cxl/cpmu.c:101:15: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
101 | val = readq(base + CPMU_CAP_REG);
| ^~~~~
| readl
In file included from <command-line>:
drivers/cxl/cpmu.c: In function 'cpmu_config_get_mask':
>> drivers/cxl/cpmu.c:416:51: error: 'struct perf_event' has no member named 'attr'
416 | return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:416:16: note: in expansion of macro 'FIELD_GET'
416 | return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
| ^~~~~~~~~
In file included from drivers/cxl/cxl.h:8,
from drivers/cxl/cxlpci.h:6,
from drivers/cxl/cpmu.c:32:
>> drivers/cxl/cpmu.c:416:51: error: 'struct perf_event' has no member named 'attr'
416 | return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
drivers/cxl/cpmu.c: In function 'cpmu_config_get_gid':
drivers/cxl/cpmu.c:421:52: error: 'struct perf_event' has no member named 'attr'
421 | return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:421:16: note: in expansion of macro 'FIELD_GET'
421 | return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
| ^~~~~~~~~
drivers/cxl/cpmu.c:421:52: error: 'struct perf_event' has no member named 'attr'
421 | return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
drivers/cxl/cpmu.c: In function 'cpmu_config_get_vid':
drivers/cxl/cpmu.c:426:52: error: 'struct perf_event' has no member named 'attr'
426 | return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:426:16: note: in expansion of macro 'FIELD_GET'
426 | return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
| ^~~~~~~~~
drivers/cxl/cpmu.c:426:52: error: 'struct perf_event' has no member named 'attr'
426 | return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
drivers/cxl/cpmu.c: In function 'cpmu_config1_get_threshold':
drivers/cxl/cpmu.c:431:51: error: 'struct perf_event' has no member named 'attr'
431 | return FIELD_GET(GENMASK_ULL(15, 0), event->attr.config1);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:431:16: note: in expansion of macro 'FIELD_GET'
431 | return FIELD_GET(GENMASK_ULL(15, 0), event->attr.config1);
--
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:441:16: note: in expansion of macro 'FIELD_GET'
441 | return FIELD_GET(BIT(17), event->attr.config1);
| ^~~~~~~~~
drivers/cxl/cpmu.c:441:40: error: 'struct perf_event' has no member named 'attr'
441 | return FIELD_GET(BIT(17), event->attr.config1);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
drivers/cxl/cpmu.c: In function 'cpmu_config1_hdm_filter_en':
drivers/cxl/cpmu.c:453:40: error: 'struct perf_event' has no member named 'attr'
453 | return FIELD_GET(BIT(14), event->attr.config1);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:453:16: note: in expansion of macro 'FIELD_GET'
453 | return FIELD_GET(BIT(14), event->attr.config1);
| ^~~~~~~~~
drivers/cxl/cpmu.c:453:40: error: 'struct perf_event' has no member named 'attr'
453 | return FIELD_GET(BIT(14), event->attr.config1);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
drivers/cxl/cpmu.c: In function 'cpmu_config2_get_hdm_decoder':
drivers/cxl/cpmu.c:458:47: error: 'struct perf_event' has no member named 'attr'
458 | return FIELD_GET(GENMASK(15, 0), event->attr.config2);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
71 | BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:61:43: note: in expansion of macro '__unsigned_scalar_typeof'
61 | #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x))
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:72:34: note: in expansion of macro '__bf_cast_unsigned'
72 | __bf_cast_unsigned(_reg, ~0ull), \
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:154:17: note: in expansion of macro '__BF_FIELD_CHECK'
154 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:458:16: note: in expansion of macro 'FIELD_GET'
458 | return FIELD_GET(GENMASK(15, 0), event->attr.config2);
| ^~~~~~~~~
drivers/cxl/cpmu.c:458:47: error: 'struct perf_event' has no member named 'attr'
458 | return FIELD_GET(GENMASK(15, 0), event->attr.config2);
| ^~
include/linux/bitfield.h:155:35: note: in definition of macro 'FIELD_GET'
155 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~
In file included from include/linux/kernel.h:21,
from arch/parisc/include/asm/bug.h:5,
from include/linux/bug.h:5,
from drivers/cxl/cpmu.c:26:
drivers/cxl/cpmu.c: In function 'cpmu_get_event_idx':
>> drivers/cxl/cpmu.c:489:56: error: 'struct perf_event' has no member named 'pmu'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:489:34: note: in expansion of macro 'pmu_to_cpmu_info'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
In file included from include/linux/bits.h:21,
from include/linux/bitops.h:6,
from drivers/cxl/cpmu.c:24:
>> drivers/cxl/cpmu.c:489:56: error: 'struct perf_event' has no member named 'pmu'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:489:34: note: in expansion of macro 'pmu_to_cpmu_info'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
>> drivers/cxl/cpmu.c:489:56: error: 'struct perf_event' has no member named 'pmu'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:489:34: note: in expansion of macro 'pmu_to_cpmu_info'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:489:34: note: in expansion of macro 'pmu_to_cpmu_info'
489 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c: In function 'cpmu_event_init':
drivers/cxl/cpmu.c:532:56: error: 'struct perf_event' has no member named 'pmu'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:532:34: note: in expansion of macro 'pmu_to_cpmu_info'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:532:56: error: 'struct perf_event' has no member named 'pmu'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:532:34: note: in expansion of macro 'pmu_to_cpmu_info'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:532:56: error: 'struct perf_event' has no member named 'pmu'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:532:34: note: in expansion of macro 'pmu_to_cpmu_info'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:532:34: note: in expansion of macro 'pmu_to_cpmu_info'
532 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
>> drivers/cxl/cpmu.c:534:14: error: 'struct perf_event' has no member named 'cpu'
534 | event->cpu = info->on_cpu;
| ^~
drivers/cxl/cpmu.c:536:18: error: 'struct perf_event' has no member named 'attr'
536 | if (event->attr.type != event->pmu->type)
| ^~
drivers/cxl/cpmu.c:536:38: error: 'struct perf_event' has no member named 'pmu'
536 | if (event->attr.type != event->pmu->type)
| ^~
>> drivers/cxl/cpmu.c:539:13: error: implicit declaration of function 'is_sampling_event' [-Werror=implicit-function-declaration]
539 | if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
| ^~~~~~~~~~~~~~~~~
>> drivers/cxl/cpmu.c:539:46: error: 'struct perf_event' has no member named 'attach_state'
539 | if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
| ^~
drivers/cxl/cpmu.c: In function 'cpmu_pmu_enable':
drivers/cxl/cpmu.c:559:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
559 | writeq(0, base + CPMU_FREEZE_REG);
| ^~~~~~
| writel
drivers/cxl/cpmu.c: In function 'cpmu_pmu_disable':
include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/cxl/cpmu.c:578:24: note: in expansion of macro 'GENMASK'
578 | writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
| ^~~~~~~
drivers/cxl/cpmu.c: In function 'cpmu_event_start':
drivers/cxl/cpmu.c:585:56: error: 'struct perf_event' has no member named 'pmu'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:585:34: note: in expansion of macro 'pmu_to_cpmu_info'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:585:56: error: 'struct perf_event' has no member named 'pmu'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:585:34: note: in expansion of macro 'pmu_to_cpmu_info'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:585:56: error: 'struct perf_event' has no member named 'pmu'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:585:34: note: in expansion of macro 'pmu_to_cpmu_info'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:585:34: note: in expansion of macro 'pmu_to_cpmu_info'
585 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
>> drivers/cxl/cpmu.c:586:43: error: 'struct perf_event' has no member named 'hw'
586 | struct hw_perf_event *hwc = &event->hw;
| ^~
In file included from arch/parisc/include/asm/bug.h:93:
>> drivers/cxl/cpmu.c:590:31: error: 'struct hw_perf_event' has no member named 'state'
590 | if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
| ^~
include/asm-generic/bug.h:110:32: note: in definition of macro 'WARN_ON_ONCE'
110 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
>> drivers/cxl/cpmu.c:590:41: error: 'PERF_HES_STOPPED' undeclared (first use in this function)
590 | if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
| ^~~~~~~~~~~~~~~~
include/asm-generic/bug.h:110:32: note: in definition of macro 'WARN_ON_ONCE'
110 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
drivers/cxl/cpmu.c:590:41: note: each undeclared identifier is reported only once for each function it appears in
590 | if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
| ^~~~~~~~~~~~~~~~
include/asm-generic/bug.h:110:32: note: in definition of macro 'WARN_ON_ONCE'
110 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
drivers/cxl/cpmu.c:593:27: error: 'struct hw_perf_event' has no member named 'state'
593 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
| ^~
include/asm-generic/bug.h:110:32: note: in definition of macro 'WARN_ON_ONCE'
110 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
>> drivers/cxl/cpmu.c:593:37: error: 'PERF_HES_UPTODATE' undeclared (first use in this function); did you mean 'PERF_EF_UPDATE'?
593 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
| ^~~~~~~~~~~~~~~~~
include/asm-generic/bug.h:110:32: note: in definition of macro 'WARN_ON_ONCE'
110 | int __ret_warn_on = !!(condition); \
| ^~~~~~~~~
drivers/cxl/cpmu.c:594:12: error: 'struct hw_perf_event' has no member named 'state'
594 | hwc->state = 0;
| ^~
In file included from drivers/cxl/cpmu.c:31:
>> drivers/cxl/cpmu.c:605:59: error: 'struct hw_perf_event' has no member named 'idx'
605 | writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
| ^~
drivers/cxl/cpmu.h:43:62: note: in definition of macro 'CPMU_FILTER_CFG_REG'
43 | #define CPMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8))
| ^
drivers/cxl/cpmu.c:608:52: error: 'struct hw_perf_event' has no member named 'idx'
608 | cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
| ^~
drivers/cxl/cpmu.h:29:55: note: in definition of macro 'CPMU_COUNTER_CFG_REG'
29 | #define CPMU_COUNTER_CFG_REG(n) (0x200 + 8 * (n))
| ^
drivers/cxl/cpmu.c:615:25: error: 'struct hw_perf_event' has no member named 'idx'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~
include/linux/bitops.h:49:32: note: in definition of macro 'bitop'
49 | ((__builtin_constant_p(nr) && \
| ^~
drivers/cxl/cpmu.c:615:13: note: in expansion of macro 'test_bit'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~~~~~~~
drivers/cxl/cpmu.c:615:25: error: 'struct hw_perf_event' has no member named 'idx'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~
include/linux/bitops.h:53:20: note: in definition of macro 'bitop'
53 | const##op(nr, addr) : op(nr, addr))
| ^~
drivers/cxl/cpmu.c:615:13: note: in expansion of macro 'test_bit'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~~~~~~~
drivers/cxl/cpmu.c:615:25: error: 'struct hw_perf_event' has no member named 'idx'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~
include/linux/bitops.h:53:35: note: in definition of macro 'bitop'
53 | const##op(nr, addr) : op(nr, addr))
| ^~
drivers/cxl/cpmu.c:615:13: note: in expansion of macro 'test_bit'
615 | if (test_bit(hwc->idx, info->conf_counter_bm)) {
| ^~~~~~~~
>> drivers/cxl/cpmu.c:616:77: error: 'struct hw_perf_event' has no member named 'event_base'
616 | cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:68:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
68 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:114:17: note: in expansion of macro '__BF_FIELD_CHECK'
114 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:616:24: note: in expansion of macro 'FIELD_PREP'
616 | cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
| ^~~~~~~~~~
>> drivers/cxl/cpmu.c:616:77: error: 'struct hw_perf_event' has no member named 'event_base'
616 | cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
| ^~
include/linux/compiler_types.h:377:23: note: in definition of macro '__compiletime_assert'
377 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:397:9: note: in expansion of macro '_compiletime_assert'
397 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:68:17: note: in expansion of macro 'BUILD_BUG_ON_MSG'
68 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:114:17: note: in expansion of macro '__BF_FIELD_CHECK'
114 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:616:24: note: in expansion of macro 'FIELD_PREP'
616 | cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
| ^~~~~~~~~~
>> drivers/cxl/cpmu.c:616:77: error: 'struct hw_perf_event' has no member named 'event_base'
616 | cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
| ^~
include/linux/bitfield.h:115:34: note: in definition of macro 'FIELD_PREP'
115 | ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
| ^~~~
drivers/cxl/cpmu.c:630:52: error: 'struct hw_perf_event' has no member named 'idx'
630 | writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
| ^~
drivers/cxl/cpmu.h:29:55: note: in definition of macro 'CPMU_COUNTER_CFG_REG'
29 | #define CPMU_COUNTER_CFG_REG(n) (0x200 + 8 * (n))
| ^
>> drivers/cxl/cpmu.c:632:9: error: implicit declaration of function 'local64_set'; did you mean 'local_set'? [-Werror=implicit-function-declaration]
632 | local64_set(&hwc->prev_count, 0);
| ^~~~~~~~~~~
| local_set
>> drivers/cxl/cpmu.c:632:25: error: 'struct hw_perf_event' has no member named 'prev_count'
632 | local64_set(&hwc->prev_count, 0);
| ^~
drivers/cxl/cpmu.c:633:46: error: 'struct hw_perf_event' has no member named 'idx'
633 | writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
| ^~
drivers/cxl/cpmu.h:46:63: note: in definition of macro 'CPMU_COUNTER_REG'
46 | #define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
| ^
>> drivers/cxl/cpmu.c:636:28: error: implicit declaration of function 'local64_read'; did you mean 'local_read'? [-Werror=implicit-function-declaration]
636 | prev_cnt = local64_read(&hwc->prev_count);
| ^~~~~~~~~~~~
| local_read
drivers/cxl/cpmu.c:636:45: error: 'struct hw_perf_event' has no member named 'prev_count'
636 | prev_cnt = local64_read(&hwc->prev_count);
| ^~
drivers/cxl/cpmu.c:637:61: error: 'struct hw_perf_event' has no member named 'idx'
637 | writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
| ^~
drivers/cxl/cpmu.h:46:63: note: in definition of macro 'CPMU_COUNTER_REG'
46 | #define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
| ^
>> drivers/cxl/cpmu.c:640:9: error: implicit declaration of function 'perf_event_update_userpage'; did you mean 'arch_perf_update_userpage'? [-Werror=implicit-function-declaration]
640 | perf_event_update_userpage(event);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
| arch_perf_update_userpage
drivers/cxl/cpmu.c: In function 'cpmu_read_counter':
drivers/cxl/cpmu.c:645:56: error: 'struct perf_event' has no member named 'pmu'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:645:34: note: in expansion of macro 'pmu_to_cpmu_info'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:645:56: error: 'struct perf_event' has no member named 'pmu'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:645:34: note: in expansion of macro 'pmu_to_cpmu_info'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:645:56: error: 'struct perf_event' has no member named 'pmu'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:645:34: note: in expansion of macro 'pmu_to_cpmu_info'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:645:34: note: in expansion of macro 'pmu_to_cpmu_info'
645 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:648:51: error: 'struct perf_event' has no member named 'hw'
648 | return readq(base + CPMU_COUNTER_REG(event->hw.idx));
| ^~
drivers/cxl/cpmu.h:46:63: note: in definition of macro 'CPMU_COUNTER_REG'
46 | #define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
| ^
drivers/cxl/cpmu.c: In function '__cpmu_read':
drivers/cxl/cpmu.c:653:56: error: 'struct perf_event' has no member named 'pmu'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:653:56: error: 'struct perf_event' has no member named 'pmu'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
vim +416 drivers/cxl/cpmu.c
413
414 static u32 cpmu_config_get_mask(struct perf_event *event)
415 {
> 416 return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
417 }
418
419 static u16 cpmu_config_get_gid(struct perf_event *event)
420 {
421 return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
422 }
423
424 static u16 cpmu_config_get_vid(struct perf_event *event)
425 {
426 return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
427 }
428
429 static u8 cpmu_config1_get_threshold(struct perf_event *event)
430 {
431 return FIELD_GET(GENMASK_ULL(15, 0), event->attr.config1);
432 }
433
434 static bool cpmu_config1_get_invert(struct perf_event *event)
435 {
436 return FIELD_GET(BIT(16), event->attr.config1);
437 }
438
439 static bool cpmu_config1_get_edge(struct perf_event *event)
440 {
441 return FIELD_GET(BIT(17), event->attr.config1);
442 }
443
444 /*
445 * CPMU specification allows for 8 filters, each with a 16 bit value...
446 * So we need to find 8x16bits to store it in.
447 * As the value used for disable is 0xffff, a separate enable switch
448 * is needed.
449 */
450
451 static bool cpmu_config1_hdm_filter_en(struct perf_event *event)
452 {
453 return FIELD_GET(BIT(14), event->attr.config1);
454 }
455
456 static u16 cpmu_config2_get_hdm_decoder(struct perf_event *event)
457 {
458 return FIELD_GET(GENMASK(15, 0), event->attr.config2);
459 }
460
461 static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
462 char *buf)
463 {
464 struct cpmu_info *info = dev_get_drvdata(dev);
465
466 return cpumap_print_to_pagebuf(true, buf, cpumask_of(info->on_cpu));
467 }
468 static DEVICE_ATTR_RO(cpumask);
469
470 static struct attribute *cpmu_cpumask_attrs[] = {
471 &dev_attr_cpumask.attr,
472 NULL
473 };
474
475 static const struct attribute_group cpmu_cpumask_group = {
476 .attrs = cpmu_cpumask_attrs,
477 };
478
479 static const struct attribute_group *cpmu_attr_groups[] = {
480 &cpmu_events,
481 &cpmu_format_group,
482 &cpmu_cpumask_group,
483 NULL
484 };
485
486 /* If counter_idx == NULL, don't try to allocate a counter. */
487 static int cpmu_get_event_idx(struct perf_event *event, int *counter_idx, int *event_idx)
488 {
> 489 struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
490 DECLARE_BITMAP(configurable_and_free, CPMU_MAX_COUNTERS);
491 struct cpmu_event *cpmu_ev;
492 u32 mask;
493 u16 gid, vid;
494 int i;
495
496 vid = cpmu_config_get_vid(event);
497 gid = cpmu_config_get_gid(event);
498 mask = cpmu_config_get_mask(event);
499
500 cpmu_ev = cpmu_find_fixed_counter_event(info, vid, gid, mask);
501 if (!IS_ERR(cpmu_ev)) {
502 if (!counter_idx)
503 return 0;
504 if (!info->hw_events[cpmu_ev->counter_idx]) {
505 *counter_idx = cpmu_ev->counter_idx;
506 return 0;
507 }
508 /* Fixed counter is in use, but maybe a configurable one? */
509 }
510
511 cpmu_ev = cpmu_find_config_counter_event(info, vid, gid, mask);
512 if (!IS_ERR(cpmu_ev)) {
513 if (!counter_idx)
514 return 0;
515
516 bitmap_andnot(configurable_and_free, info->conf_counter_bm,
517 info->used_counter_bm, CPMU_MAX_COUNTERS);
518
519 i = find_first_bit(configurable_and_free, CPMU_MAX_COUNTERS);
520 if (i == CPMU_MAX_COUNTERS)
521 return -EINVAL;
522
523 *counter_idx = i;
524 return 0;
525 }
526
527 return -EINVAL;
528 }
529
530 static int cpmu_event_init(struct perf_event *event)
531 {
532 struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
533
> 534 event->cpu = info->on_cpu;
535 /* Top level type sanity check - is this a Hardware Event being requested */
536 if (event->attr.type != event->pmu->type)
537 return -ENOENT;
538
> 539 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
540 return -EOPNOTSUPP;
541 /* TODO: Validation of any filter */
542
543 /*
544 * Verify that it is possible to count what was requested. Either must
545 * be a fixed counter that is a precise match or a configurable counter
546 * where this is a subset.
547 */
548 return cpmu_get_event_idx(event, NULL, NULL);
549 }
550
551 static void cpmu_pmu_enable(struct pmu *pmu)
552 {
553 struct cpmu_info *info = pmu_to_cpmu_info(pmu);
554 void __iomem *base = info->base;
555
556 /* We don't have a global enable, but we 'might' have a global freeze which we can use */
557 if (info->freeze_for_enable) {
558 /* Can assume frozen at this stage */
559 writeq(0, base + CPMU_FREEZE_REG);
560
561 return;
562 }
563 }
564
565 static void cpmu_pmu_disable(struct pmu *pmu)
566 {
567 struct cpmu_info *info = pmu_to_cpmu_info(pmu);
568 void __iomem *base = info->base;
569
570 if (info->freeze_for_enable) {
571 /*
572 * Whilst bits above number of counters are RsvdZ
573 * they are unlikely to be repurposed given
574 * number of counters is allowed to be 64 leaving
575 * no reserved bits. Hence this is only slightly
576 * naughty.
577 */
578 writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
579 return;
580 }
581 }
582
583 static void cpmu_event_start(struct perf_event *event, int flags)
584 {
585 struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> 586 struct hw_perf_event *hwc = &event->hw;
587 void __iomem *base = info->base;
588 u64 cfg, prev_cnt;
589
> 590 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
591 return;
592
> 593 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
594 hwc->state = 0;
595
596 /*
597 * Currently only hdm filter control is implemnted, this code will
598 * want generalizing when more filters are added.
599 */
600 if (info->filter_hdm) {
601 if (cpmu_config1_hdm_filter_en(event))
602 cfg = cpmu_config2_get_hdm_decoder(event);
603 else
604 cfg = GENMASK(15, 0);
> 605 writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
606 }
607
608 cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
609 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
610 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
611 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
612 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
613
614 /* Fixed purpose counters have next two fields RO */
615 if (test_bit(hwc->idx, info->conf_counter_bm)) {
616 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
617 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
618 }
619 cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
620 /*
621 * For events that generate only 1 count per clock the CXL 3.0 spec
622 * states the threshold shall be set to 1 but if set to 0 it will
623 * count the raw value anwyay?
624 * There is no definition of what events will count multiple per cycle
625 * and hence to which non 1 values of threshold can apply.
626 * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
627 */
628 cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
629 cpmu_config1_get_threshold(event));
630 writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
631
632 local64_set(&hwc->prev_count, 0);
633 writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
634
635 if (flags & PERF_EF_RELOAD) {
636 prev_cnt = local64_read(&hwc->prev_count);
637 writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
638 }
639
640 perf_event_update_userpage(event);
641 }
642
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-03-24 21:12 ` kernel test robot
@ 2023-03-24 21:42 ` kernel test robot
2023-03-24 22:03 ` kernel test robot
` (2 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2023-03-24 21:42 UTC (permalink / raw)
To: Jonathan Cameron, Liang Kan, linux-cxl, peterz
Cc: oe-kbuild-all, mingo, acme, mark.rutland, will, dan.j.williams,
linuxarm, linux-perf-users, linux-kernel, Davidlohr Bueso,
Dave Jiang
Hi Jonathan,
I love your patch! Yet something to improve:
[auto build test ERROR on acme/perf/core]
[also build test ERROR on tip/perf/core cxl/next cxl/pending linus/master v6.3-rc3 next-20230324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
patch link: https://lore.kernel.org/r/20230324171313.18448-5-Jonathan.Cameron%40huawei.com
patch subject: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
config: alpha-buildonly-randconfig-r006-20230322 (https://download.01.org/0day-ci/archive/20230325/202303250549.dFFcvnrK-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
git checkout a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=alpha olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=alpha SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303250549.dFFcvnrK-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:653:56: error: 'struct perf_event' has no member named 'pmu'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:653:56: error: 'struct perf_event' has no member named 'pmu'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:653:34: note: in expansion of macro 'pmu_to_cpmu_info'
653 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:654:43: error: 'struct perf_event' has no member named 'hw'
654 | struct hw_perf_event *hwc = &event->hw;
| ^~
drivers/cxl/cpmu.c:658:45: error: 'struct hw_perf_event' has no member named 'prev_count'
658 | prev_cnt = local64_read(&hwc->prev_count);
| ^~
arch/alpha/include/asm/local.h:14:44: note: in definition of macro 'local_read'
14 | #define local_read(l) atomic_long_read(&(l)->a)
| ^
drivers/cxl/cpmu.c:658:28: note: in expansion of macro 'local64_read'
658 | prev_cnt = local64_read(&hwc->prev_count);
| ^~~~~~~~~~~~
In file included from include/linux/atomic.h:82,
from include/linux/rcupdate.h:25,
from include/linux/rculist.h:11:
drivers/cxl/cpmu.c:660:38: error: 'struct hw_perf_event' has no member named 'prev_count'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~
include/linux/atomic/atomic-instrumented.h:2049:16: note: in definition of macro 'cmpxchg_local'
2049 | typeof(ptr) __ai_ptr = (ptr); \
| ^~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:38: error: 'struct hw_perf_event' has no member named 'prev_count'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~
include/linux/atomic/atomic-instrumented.h:2049:33: note: in definition of macro 'cmpxchg_local'
2049 | typeof(ptr) __ai_ptr = (ptr); \
| ^~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
>> include/linux/atomic/atomic-instrumented.h:2050:50: error: invalid type argument of unary '*' (have 'int')
2050 | instrument_atomic_write(__ai_ptr, sizeof(*__ai_ptr)); \
| ^~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
>> include/linux/atomic/atomic-instrumented.h:2050:33: warning: passing argument 1 of 'instrument_atomic_write' makes pointer from integer without a cast [-Wint-conversion]
2050 | instrument_atomic_write(__ai_ptr, sizeof(*__ai_ptr)); \
| ^~~~~~~~
| |
| int
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
In file included from include/linux/atomic/atomic-instrumented.h:22:
include/linux/instrumented.h:85:74: note: expected 'const volatile void *' but argument is of type 'int'
85 | static __always_inline void instrument_atomic_write(const volatile void *v, size_t size)
| ~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/alpha/include/asm/atomic.h:7,
from include/linux/atomic.h:7:
>> arch/alpha/include/asm/cmpxchg.h:22:20: error: invalid type argument of unary '*' (have 'int')
22 | __typeof__(*(ptr)) _o_ = (o); \
| ^~~~~~
include/linux/atomic/atomic-instrumented.h:2051:9: note: in expansion of macro 'arch_cmpxchg_local'
2051 | arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
arch/alpha/include/asm/cmpxchg.h:23:20: error: invalid type argument of unary '*' (have 'int')
23 | __typeof__(*(ptr)) _n_ = (n); \
| ^~~~~~
include/linux/atomic/atomic-instrumented.h:2051:9: note: in expansion of macro 'arch_cmpxchg_local'
2051 | arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
arch/alpha/include/asm/cmpxchg.h:24:21: error: invalid type argument of unary '*' (have 'int')
24 | (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
| ^~~~~~
include/linux/atomic/atomic-instrumented.h:2051:9: note: in expansion of macro 'arch_cmpxchg_local'
2051 | arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
arch/alpha/include/asm/cmpxchg.h:26:50: error: invalid type argument of unary '*' (have 'int')
26 | sizeof(*(ptr))); \
| ^~~~~~
include/linux/atomic/atomic-instrumented.h:2051:9: note: in expansion of macro 'arch_cmpxchg_local'
2051 | arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
>> arch/alpha/include/asm/cmpxchg.h:24:46: warning: passing argument 1 of '__cmpxchg_local' makes pointer from integer without a cast [-Wint-conversion]
24 | (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
| ^~~~~
| |
| int
include/linux/atomic/atomic-instrumented.h:2051:9: note: in expansion of macro 'arch_cmpxchg_local'
2051 | arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~~
arch/alpha/include/asm/local.h:56:10: note: in expansion of macro 'cmpxchg_local'
56 | (cmpxchg_local(&((l)->a.counter), (o), (n)))
| ^~~~~~~~~~~~~
include/asm-generic/local64.h:45:34: note: in expansion of macro 'local_cmpxchg'
45 | #define local64_cmpxchg(l, o, n) local_cmpxchg((&(l)->a), (o), (n))
| ^~~~~~~~~~~~~
drivers/cxl/cpmu.c:660:18: note: in expansion of macro 'local64_cmpxchg'
660 | } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
| ^~~~~~~~~~~~~~~
arch/alpha/include/asm/xchg.h:229:30: note: expected 'volatile void *' but argument is of type 'int'
229 | ____cmpxchg(, volatile void *ptr, unsigned long old, unsigned long new,
| ~~~~~~~~~~~~~~~^~~
arch/alpha/include/asm/cmpxchg.h:10:69: note: in definition of macro '____cmpxchg'
10 | #define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
| ^~~~
drivers/cxl/cpmu.c:670:34: error: 'struct perf_event' has no member named 'count'
670 | local64_add(delta, &event->count);
| ^~
arch/alpha/include/asm/local.h:18:48: note: in definition of macro 'local_add'
18 | #define local_add(i,l) atomic_long_add((i),(&(l)->a))
| ^
drivers/cxl/cpmu.c:670:9: note: in expansion of macro 'local64_add'
670 | local64_add(delta, &event->count);
| ^~~~~~~~~~~
drivers/cxl/cpmu.c: In function 'cpmu_event_stop':
drivers/cxl/cpmu.c:680:56: error: 'struct perf_event' has no member named 'pmu'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/container_of.h:19:33: note: in definition of macro 'container_of'
19 | void *__mptr = (void *)(ptr); \
| ^~~
drivers/cxl/cpmu.c:680:34: note: in expansion of macro 'pmu_to_cpmu_info'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:680:56: error: 'struct perf_event' has no member named 'pmu'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:680:34: note: in expansion of macro 'pmu_to_cpmu_info'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:680:56: error: 'struct perf_event' has no member named 'pmu'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:21:23: note: in expansion of macro '__same_type'
21 | __same_type(*(ptr), void), \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:680:34: note: in expansion of macro 'pmu_to_cpmu_info'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer
338 | #define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:78:56: note: in definition of macro '__static_assert'
78 | #define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
| ^~~~
include/linux/container_of.h:20:9: note: in expansion of macro 'static_assert'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~~~
include/linux/container_of.h:20:23: note: in expansion of macro '__same_type'
20 | static_assert(__same_type(*(ptr), ((type *)0)->member) || \
| ^~~~~~~~~~~
drivers/cxl/cpmu.c:82:32: note: in expansion of macro 'container_of'
82 | #define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
| ^~~~~~~~~~~~
drivers/cxl/cpmu.c:680:34: note: in expansion of macro 'pmu_to_cpmu_info'
680 | struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
| ^~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:682:43: error: 'struct perf_event' has no member named 'hw'
682 | struct hw_perf_event *hwc = &event->hw;
| ^~
drivers/cxl/cpmu.c:686:25: error: 'struct hw_perf_event' has no member named 'state'
686 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
vim +2050 include/linux/atomic/atomic-instrumented.h
0aa7be05d83cc5 include/linux/atomic/atomic-instrumented.h Uros Bizjak 2022-05-15 2046
aa525d063851a9 include/asm-generic/atomic-instrumented.h Mark Rutland 2018-09-04 2047 #define cmpxchg_local(ptr, ...) \
b06ed71a624ba0 include/asm-generic/atomic-instrumented.h Dmitry Vyukov 2018-01-29 2048 ({ \
df79ed2c064363 include/asm-generic/atomic-instrumented.h Mark Rutland 2018-07-16 2049 typeof(ptr) __ai_ptr = (ptr); \
ed8af2e4d2a71b include/asm-generic/atomic-instrumented.h Marco Elver 2020-01-21 @2050 instrument_atomic_write(__ai_ptr, sizeof(*__ai_ptr)); \
aa525d063851a9 include/asm-generic/atomic-instrumented.h Mark Rutland 2018-09-04 2051 arch_cmpxchg_local(__ai_ptr, __VA_ARGS__); \
b06ed71a624ba0 include/asm-generic/atomic-instrumented.h Dmitry Vyukov 2018-01-29 2052 })
b06ed71a624ba0 include/asm-generic/atomic-instrumented.h Dmitry Vyukov 2018-01-29 2053
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-03-24 21:12 ` kernel test robot
2023-03-24 21:42 ` kernel test robot
@ 2023-03-24 22:03 ` kernel test robot
2023-03-24 22:03 ` kernel test robot
2023-03-27 17:07 ` Liang, Kan
4 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2023-03-24 22:03 UTC (permalink / raw)
To: Jonathan Cameron, Liang Kan, linux-cxl, peterz
Cc: llvm, oe-kbuild-all, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
Hi Jonathan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on acme/perf/core]
[also build test WARNING on tip/perf/core cxl/next cxl/pending linus/master v6.3-rc3 next-20230324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
patch link: https://lore.kernel.org/r/20230324171313.18448-5-Jonathan.Cameron%40huawei.com
patch subject: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20230325/202303250546.ijiFKIpM-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
git checkout a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303250546.ijiFKIpM-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/cxl/cpmu.c:101:8: error: implicit declaration of function 'readq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
val = readq(base + CPMU_CAP_REG);
^
drivers/cxl/cpmu.c:559:3: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(0, base + CPMU_FREEZE_REG);
^
drivers/cxl/cpmu.c:578:3: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
^
>> drivers/cxl/cpmu.c:578:10: warning: shift count is negative [-Wshift-count-negative]
writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
^~~~~~~~~~~~~~
include/linux/bits.h:37:31: note: expanded from macro 'GENMASK'
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~~~~~~~
include/linux/bits.h:35:11: note: expanded from macro '__GENMASK'
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^ ~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/cxl/cpmu.c:605:3: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
^
drivers/cxl/cpmu.c:608:8: error: implicit declaration of function 'readq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
^
drivers/cxl/cpmu.c:630:2: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
^
drivers/cxl/cpmu.c:648:9: error: implicit declaration of function 'readq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
return readq(base + CPMU_COUNTER_REG(event->hw.idx));
^
drivers/cxl/cpmu.c:689:8: error: implicit declaration of function 'readq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
^
drivers/cxl/cpmu.c:692:2: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
^
drivers/cxl/cpmu.c:709:2: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(0, base + CPMU_EVENT_CAP_REG(idx));
^
drivers/cxl/cpmu.c:761:15: error: implicit declaration of function 'readq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
overflowed = readq(base + CPMU_OVERFLOW_REG);
^
drivers/cxl/cpmu.c:780:2: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
writeq(overflowed, base + CPMU_OVERFLOW_REG);
^
1 warning and 12 errors generated.
vim +578 drivers/cxl/cpmu.c
564
565 static void cpmu_pmu_disable(struct pmu *pmu)
566 {
567 struct cpmu_info *info = pmu_to_cpmu_info(pmu);
568 void __iomem *base = info->base;
569
570 if (info->freeze_for_enable) {
571 /*
572 * Whilst bits above number of counters are RsvdZ
573 * they are unlikely to be repurposed given
574 * number of counters is allowed to be 64 leaving
575 * no reserved bits. Hence this is only slightly
576 * naughty.
577 */
> 578 writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
579 return;
580 }
581 }
582
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
` (2 preceding siblings ...)
2023-03-24 22:03 ` kernel test robot
@ 2023-03-24 22:03 ` kernel test robot
2023-03-27 17:07 ` Liang, Kan
4 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2023-03-24 22:03 UTC (permalink / raw)
To: Jonathan Cameron, Liang Kan, linux-cxl, peterz
Cc: oe-kbuild-all, mingo, acme, mark.rutland, will, dan.j.williams,
linuxarm, linux-perf-users, linux-kernel, Davidlohr Bueso,
Dave Jiang
Hi Jonathan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on acme/perf/core]
[also build test WARNING on tip/perf/core cxl/next cxl/pending linus/master v6.3-rc3 next-20230324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
patch link: https://lore.kernel.org/r/20230324171313.18448-5-Jonathan.Cameron%40huawei.com
patch subject: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
config: i386-randconfig-a001 (https://download.01.org/0day-ci/archive/20230325/202303250510.RNVcynwI-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
git checkout a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 olddefconfig
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/cxl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303250510.RNVcynwI-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/cxl/cpmu.c: In function 'cpmu_parse_caps':
drivers/cxl/cpmu.c:101:15: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
101 | val = readq(base + CPMU_CAP_REG);
| ^~~~~
| readl
drivers/cxl/cpmu.c: In function 'cpmu_pmu_enable':
drivers/cxl/cpmu.c:559:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
559 | writeq(0, base + CPMU_FREEZE_REG);
| ^~~~~~
| writel
In file included from include/linux/bitops.h:6,
from drivers/cxl/cpmu.c:24:
drivers/cxl/cpmu.c: In function 'cpmu_pmu_disable':
>> include/linux/bits.h:35:18: warning: right shift count is negative [-Wshift-count-negative]
35 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/bits.h:37:38: note: in expansion of macro '__GENMASK'
37 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/cxl/cpmu.c:578:24: note: in expansion of macro 'GENMASK'
578 | writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
| ^~~~~~~
cc1: some warnings being treated as errors
vim +35 include/linux/bits.h
295bcca84916cb Rikard Falkeborn 2020-04-06 32
295bcca84916cb Rikard Falkeborn 2020-04-06 33 #define __GENMASK(h, l) \
95b980d62d52c4 Masahiro Yamada 2019-07-16 34 (((~UL(0)) - (UL(1) << (l)) + 1) & \
95b980d62d52c4 Masahiro Yamada 2019-07-16 @35 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
295bcca84916cb Rikard Falkeborn 2020-04-06 36 #define GENMASK(h, l) \
295bcca84916cb Rikard Falkeborn 2020-04-06 37 (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
8bd9cb51daac89 Will Deacon 2018-06-19 38
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices
2023-03-24 21:01 ` kernel test robot
@ 2023-03-27 15:50 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-27 15:50 UTC (permalink / raw)
To: kernel test robot
Cc: Liang Kan, linux-cxl, peterz, llvm, oe-kbuild-all, mingo, acme,
mark.rutland, will, dan.j.williams, linuxarm, linux-perf-users,
linux-kernel, Davidlohr Bueso, Dave Jiang
On Sat, 25 Mar 2023 05:01:09 +0800
kernel test robot <lkp@intel.com> wrote:
> Hi Jonathan,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on acme/perf/core]
> [also build test ERROR on tip/perf/core]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
> base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
> patch link: https://lore.kernel.org/r/20230324171313.18448-4-Jonathan.Cameron%40huawei.com
> patch subject: [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices
> config: arm-randconfig-r023-20230322 (https://download.01.org/0day-ci/archive/20230325/202303250419.FANh4fIC-lkp@intel.com/config)
> compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 67409911353323ca5edf2049ef0df54132fa1ca7)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm cross compiling tool for clang build
> # apt-get install binutils-arm-linux-gnueabi
> # https://github.com/intel-lab-lkp/linux/commit/ab99ab31e5c4aa9f68425f3505f22a790d64bfe9
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
> git checkout ab99ab31e5c4aa9f68425f3505f22a790d64bfe9
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/cxl/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Link: https://lore.kernel.org/oe-kbuild-all/202303250419.FANh4fIC-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> >> drivers/cxl/core/port.c:60:20: error: use of undeclared identifier 'cxl_cpmu_type'; did you mean 'cxl_bus_type'?
> if (dev->type == &cxl_cpmu_type)
> ^~~~~~~~~~~~~
Definition is under the CXL_REGION ifdef and it shouldn't be.
Moved it up to alongside the nvdimm ones.
> cxl_bus_type
> drivers/cxl/cxl.h:732:24: note: 'cxl_bus_type' declared here
> extern struct bus_type cxl_bus_type;
> ^
> 1 error generated.
>
>
> vim +60 drivers/cxl/core/port.c
>
> 40
> 41 static int cxl_device_id(const struct device *dev)
> 42 {
> 43 if (dev->type == &cxl_nvdimm_bridge_type)
> 44 return CXL_DEVICE_NVDIMM_BRIDGE;
> 45 if (dev->type == &cxl_nvdimm_type)
> 46 return CXL_DEVICE_NVDIMM;
> 47 if (dev->type == CXL_PMEM_REGION_TYPE())
> 48 return CXL_DEVICE_PMEM_REGION;
> 49 if (dev->type == CXL_DAX_REGION_TYPE())
> 50 return CXL_DEVICE_DAX_REGION;
> 51 if (is_cxl_port(dev)) {
> 52 if (is_cxl_root(to_cxl_port(dev)))
> 53 return CXL_DEVICE_ROOT;
> 54 return CXL_DEVICE_PORT;
> 55 }
> 56 if (is_cxl_memdev(dev))
> 57 return CXL_DEVICE_MEMORY_EXPANDER;
> 58 if (dev->type == CXL_REGION_TYPE())
> 59 return CXL_DEVICE_REGION;
> > 60 if (dev->type == &cxl_cpmu_type)
> 61 return CXL_DEVICE_CPMU;
> 62 return 0;
> 63 }
> 64
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 21:12 ` kernel test robot
@ 2023-03-27 15:50 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-27 15:50 UTC (permalink / raw)
To: kernel test robot
Cc: Liang Kan, linux-cxl, peterz, oe-kbuild-all, mingo, acme,
mark.rutland, will, dan.j.williams, linuxarm, linux-perf-users,
linux-kernel, Davidlohr Bueso, Dave Jiang
On Sat, 25 Mar 2023 05:12:01 +0800
kernel test robot <lkp@intel.com> wrote:
> Hi Jonathan,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on acme/perf/core]
> [also build test ERROR on tip/perf/core cxl/next cxl/pending linus/master v6.3-rc3 next-20230324]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
> base: https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/core
> patch link: https://lore.kernel.org/r/20230324171313.18448-5-Jonathan.Cameron%40huawei.com
> patch subject: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
> config: parisc-randconfig-r036-20230324 (https://download.01.org/0day-ci/archive/20230325/202303250523.JdddC4Ld-lkp@intel.com/config)
> compiler: hppa-linux-gcc (GCC) 12.1.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/intel-lab-lkp/linux/commit/a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Jonathan-Cameron/cxl-Add-function-to-count-regblocks-of-a-given-type/20230325-011827
> git checkout a04f0052a1fa10bda54569c8c7b3ab7fe60ca975
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=parisc olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=parisc SHELL=/bin/bash drivers/cxl/
Wow. This wasn't one of my best :(
Anyhow thanks for the reports + detailed build description.
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Link: https://lore.kernel.org/oe-kbuild-all/202303250523.JdddC4Ld-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> drivers/cxl/cpmu.c: In function 'cpmu_parse_caps':
> drivers/cxl/cpmu.c:101:15: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
> 101 | val = readq(base + CPMU_CAP_REG);
Added include of linux/io-64-non-atomic-lo-hi.h
> | ^~~~~
> | readl
> In file included from <command-line>:
> drivers/cxl/cpmu.c: In function 'cpmu_config_get_mask':
> >> drivers/cxl/cpmu.c:416:51: error: 'struct perf_event' has no member named 'attr'
> 416 | return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
Added depends on PERF_EVENTS
which I'd missed because it comes for free if a driver is under the drivers/perf/Kconfig menu.
> drivers/cxl/cpmu.c:578:24: note: in expansion of macro 'GENMASK'
> 578 | writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
GENMASK_ULL() here and a couple of other places where it's not a compile
time constant.
> >> drivers/cxl/cpmu.c:632:9: error: implicit declaration of function 'local64_set'; did you mean 'local_set'? [-Werror=implicit-function-declaration]
> 632 | local64_set(&hwc->prev_count, 0);
> | ^~~~~~~~~~~
> | local_set
...
> >> drivers/cxl/cpmu.c:636:28: error: implicit declaration of function 'local64_read'; did you mean 'local_read'? [-Werror=implicit-function-declaration]
> 636 | prev_cnt = local64_read(&hwc->prev_count);
> | ^~~~~~~~~~~~
> | local_read
> drivers/cxl/cpmu.c:636:45: error: 'struct hw_perf_event' has no member named 'prev_count'
> 636 | prev_cnt = local64_read(&hwc->prev_count);
> | ^~
> drivers/cxl/cpmu.c:637:61: error: 'struct hw_perf_event' has no member named 'idx'
> 637 | writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
> | ^~
> drivers/cxl/cpmu.h:46:63: note: in definition of macro 'CPMU_COUNTER_REG'
> 46 | #define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
> | ^
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-24 17:13 ` [PATCH v2 2/5] perf: Allow a PMU to have a parent Jonathan Cameron
@ 2023-03-27 17:04 ` Liang, Kan
2023-03-28 10:54 ` Jonathan Cameron
0 siblings, 1 reply; 20+ messages in thread
From: Liang, Kan @ 2023-03-27 17:04 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> Some PMUs have well defined parents such as PCI devices.
> As the device_initialize() and device_add() are all within
> pmu_dev_alloc() which is called from perf_pmu_register()
> there is no opportunity to set the parent from within a driver.
>
> Add a struct device *parent field to struct pmu and use that
> to set the parent.
Why we want a PMU parent? Maybe I missed it. I don't see that the parent
is used anywhere.
Thanks,
Kan
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> include/linux/perf_event.h | 1 +
> kernel/events/core.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index d5628a7b5eaa..b99db1eda72c 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -303,6 +303,7 @@ struct pmu {
>
> struct module *module;
> struct device *dev;
> + struct device *parent;
> const struct attribute_group **attr_groups;
> const struct attribute_group **attr_update;
> const char *name;
> diff --git a/kernel/events/core.c b/kernel/events/core.c
> index fb3e436bcd4a..a84c282221f2 100644
> --- a/kernel/events/core.c
> +++ b/kernel/events/core.c
> @@ -11367,6 +11367,7 @@ static int pmu_dev_alloc(struct pmu *pmu)
>
> dev_set_drvdata(pmu->dev, pmu);
> pmu->dev->bus = &pmu_bus;
> + pmu->dev->parent = pmu->parent;
> pmu->dev->release = pmu_dev_release;
>
> ret = dev_set_name(pmu->dev, "%s", pmu->name);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
` (3 preceding siblings ...)
2023-03-24 22:03 ` kernel test robot
@ 2023-03-27 17:07 ` Liang, Kan
2023-03-29 13:11 ` Jonathan Cameron
4 siblings, 1 reply; 20+ messages in thread
From: Liang, Kan @ 2023-03-27 17:07 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, peterz
Cc: mingo, acme, mark.rutland, will, dan.j.williams, linuxarm,
linux-perf-users, linux-kernel, Davidlohr Bueso, Dave Jiang
On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> CXL rev 3.0 introduces a standard performance monitoring hardware
> block to CXL. Instances are discovered using CXL Register Locator DVSEC
> entries. Each CXL component may have multiple PMUs.
>
> This initial driver supports on a subset of types of counter.
> It support counters that are either fixed or configurable, but requires
> that they support the ability to freeze and write value whilst frozen.
>
> Development done with QEMU model which will be posted shortly.
>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
>
> Thanks to Kan Liang for detailed review and discussion of the configurability
> description to userspace. Note that complexity is left for a future patch set.
> v2:
> - Split the events list in to configurable and fixed cases.
> - Add utility functions to search each list.
> - Allow fallback to configurable counter if fixed counter for same
> thing is already in use.
> - Fix check of filter.
> - Add a macro for the CXL defined events and use the
> PCI_DVSEC_VENDOR_ID_CXL define. Sure this isn't DVSEC but the
> value was first used there and naming that define is complex for
> fun legal reasons.
> - Verify the event capability for what is requested is possible
> in cpmu_event_init() to error out earlier if not.
> - Drop an unnecessary check on enable in cpmu_pmu_enable()
> - Use bitmap manipulation to make it cheaper to find an unused counter.
> ---
> drivers/cxl/Kconfig | 12 +
> drivers/cxl/Makefile | 1 +
> drivers/cxl/cpmu.c | 937 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 950 insertions(+)
>
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index ff4e78117b31..d68fc5769c58 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -139,4 +139,16 @@ config CXL_REGION_INVALIDATION_TEST
> If unsure, or if this kernel is meant for production environments,
> say N.
>
> +config CXL_CPMU
> + tristate "CXL Performance Monitoring Unit"
> + default CXL_BUS
> + help
> + Support performance monitoring as defined in CXL rev 3.0
> + section 13.2: Performance Monitoring. CXL components may have
> + one or more CXL Performance Monitoring Units (CPMUs).
> +
> + Say 'y/m' to enable a driver that will attach to performance
> + monitoring units and provide standard perf based interfaces.
> +
> + If unsure say 'm'.
> endif
> diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
> index db321f48ba52..024bb739554b 100644
> --- a/drivers/cxl/Makefile
> +++ b/drivers/cxl/Makefile
> @@ -5,6 +5,7 @@ obj-$(CONFIG_CXL_MEM) += cxl_mem.o
> obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
> obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
> obj-$(CONFIG_CXL_PORT) += cxl_port.o
> +obj-$(CONFIG_CXL_CPMU) += cpmu.o
>
> cxl_mem-y := mem.o
> cxl_pci-y := pci.o
> diff --git a/drivers/cxl/cpmu.c b/drivers/cxl/cpmu.c
> new file mode 100644
> index 000000000000..7a259f9de05e
> --- /dev/null
> +++ b/drivers/cxl/cpmu.c
> @@ -0,0 +1,937 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/*
> + * Copyright(c) 2023 Huawei
> + *
> + * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
> + * called the CXL PMU, or CPMU. In order to allow a high degree of
> + * implementation flexibility the specification provides a wide range of
> + * options all of which are self describing.
> + *
> + * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
> + *
> + * TODO
> + * o Discoverability of counters. Allow perftool to provide summed counters
> + * and vendor defined counters.
> + * o Support free running counters - copy the Intel uncore PMU handling for these.
> + * o CPMUs which do not support freeze.
> + * o Add filter validation in cpmu_event_init() so problems are detected earlier.
> + * o Reject configurations that the hardware is ignoring
> + * (e.g. invert when not invertible)
> + * o Support CPMUs with no interrupts using an HRTIMER.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/bits.h>
> +#include <linux/bug.h>
> +#include <linux/device.h>
> +#include <linux/list.h>
> +#include <linux/pci.h>
> +#include <linux/perf_event.h>
> +#include "cpmu.h"
> +#include "cxlpci.h"
> +#include "cxl.h"
> +
> +/* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
> +#define CPMU_GID_CLOCK_TICKS 0x00
> +#define CPMU_GID_D2H_REQ 0x0010
> +#define CPMU_GID_D2H_RSP 0x0011
> +#define CPMU_GID_H2D_REQ 0x0012
> +#define CPMU_GID_H2D_RSP 0x0013
> +#define CPMU_GID_CACHE_DATA 0x0014
> +#define CPMU_GID_M2S_REQ 0x0020
> +#define CPMU_GID_M2S_RWD 0x0021
> +#define CPMU_GID_M2S_BIRSP 0x0022
> +#define CPMU_GID_S2M_BISNP 0x0023
> +#define CPMU_GID_S2M_NDR 0x0024
> +#define CPMU_GID_S2M_DRS 0x0025
> +#define CPMU_GID_DDR 0x8000
> +
> +static int cpmu_cpuhp_state_num;
> +
> +struct cpmu_event {
> + u16 vid;
> + u16 gid;
> + u32 msk;
> + union {
> + int counter_idx; /* fixed counters */
> + int event_idx; /* configurable counters */
> + };
> + struct list_head node;
> +};
> +
> +#define CPMU_MAX_COUNTERS 64
> +struct cpmu_info {
> + struct pmu pmu;
> + void __iomem *base;
> + struct perf_event **hw_events;
> + struct list_head events_configurable;
> + struct list_head events_fixed;
> + DECLARE_BITMAP(used_counter_bm, CPMU_MAX_COUNTERS);
> + DECLARE_BITMAP(conf_counter_bm, CPMU_MAX_COUNTERS);
> + u16 counter_width;
> + u8 num_counters;
> + u8 num_event_capabilities;
> + int on_cpu;
> + struct hlist_node node;
> + bool freeze_for_enable;
> + bool filter_hdm;
> + int irq;
> +};
> +
> +#define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
> +
> +/*
> + * All CPMU counters are discoverable via the Event Capabilities Registers.
> + * Each Event Capability register contains a a VID / GroupID.
> + * A counter may then count any combination (by summing) of events in
> + * that group which are in the Supported Events Bitmask.
> + * However, there are some complexities to the scheme.
> + * - Fixed function counters refer to an Event Capabilities register.
> + * That event capability register is not then used for Configurable
> + * counters.
> + */
> +static int cpmu_parse_caps(struct device *dev, struct cpmu_info *info)
> +{
> + DECLARE_BITMAP(fixed_counter_event_cap_bm, 32) = {0};
> + void __iomem *base = info->base;
> + u64 val, eval;
> + int i;
> +
> + val = readq(base + CPMU_CAP_REG);
> + info->freeze_for_enable = FIELD_GET(CPMU_CAP_WRITEABLE_WHEN_FROZEN, val) &
> + FIELD_GET(CPMU_CAP_FREEZE, val);
> + if (!info->freeze_for_enable) {
> + dev_err(dev, "Driver does not support CPMUs that do not support freeze for enable\n");
> + return -ENODEV;
> + }
> +
> + info->num_counters = FIELD_GET(CPMU_CAP_NUM_COUNTERS_MSK, val) + 1;
> + info->counter_width = FIELD_GET(CPMU_CAP_COUNTER_WIDTH_MSK, val);
> + info->num_event_capabilities = FIELD_GET(CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;
> +
> + info->filter_hdm = FIELD_GET(CPMU_CAP_FILTERS_SUP_MSK, val) & CPMU_FILTER_HDM;
> + if (FIELD_GET(CPMU_CAP_INT, val))
> + info->irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
> + else
> + info->irq = -1;
> +
> + /* First handle fixed function counters; note if configurable counters found */
> + for (i = 0; i < info->num_counters; i++) {
> + struct cpmu_event *cpmu_ev;
> + u32 events_msk;
> + u8 group_idx;
> +
> + val = readq(base + CPMU_COUNTER_CFG_REG(i));
> +
> + if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) ==
> + CPMU_COUNTER_CFG_TYPE_CONFIGURABLE) {
> + set_bit(i, info->conf_counter_bm);
> + }
> +
> + if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) !=
> + CPMU_COUNTER_CFG_TYPE_FIXED_FUN)
> + continue;
> +
> + /* In this case we know which fields are const */
> + group_idx = FIELD_GET(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);
> + events_msk = FIELD_GET(CPMU_COUNTER_CFG_EVENTS_MSK, val);
> + eval = readq(base + CPMU_EVENT_CAP_REG(group_idx));
> + cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
> + if (!cpmu_ev)
> + return -ENOMEM;
> +
> + cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
> + cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
> + /* For a fixed purpose counter use the events mask from the counter CFG */
> + cpmu_ev->msk = events_msk;
> + cpmu_ev->counter_idx = i;
> + /* This list add is never unwound as all entries deleted on remove */
> + list_add(&cpmu_ev->node, &info->events_fixed);
> + /*
> + * Configurable counters must not use an Event Capability registers that
> + * is in use for a Fixed counter
> + */
> + set_bit(group_idx, fixed_counter_event_cap_bm);
> + }
> +
> + if (!bitmap_empty(info->conf_counter_bm, CPMU_MAX_COUNTERS)) {
> + struct cpmu_event *cpmu_ev;
> + int j;
> + /* Walk event capabilities unused by fixed counters */
> + for_each_clear_bit(j, fixed_counter_event_cap_bm,
> + info->num_event_capabilities) {
> + cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
> + if (!cpmu_ev)
> + return -ENOMEM;
> +
> + eval = readq(base + CPMU_EVENT_CAP_REG(j));
> + cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
> + cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
> + cpmu_ev->msk = FIELD_GET(CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);
> + cpmu_ev->event_idx = j;
> + list_add(&cpmu_ev->node, &info->events_configurable);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static ssize_t cpmu_event_sysfs_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct perf_pmu_events_attr *pmu_attr =
> + container_of(attr, struct perf_pmu_events_attr, attr);
> +
> + return sysfs_emit(buf, "config=%#llx\n", pmu_attr->id);
> +}
> +
> +#define CPMU_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
> + PMU_EVENT_ATTR_ID(_name, cpmu_event_sysfs_show, \
> + ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
> +
> +/* For CXL spec defined events */
> +#define CPMU_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
> + CPMU_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
> +
> +static struct attribute *cpmu_event_attrs[] = {
> + CPMU_PMU_EVENT_CXL_ATTR(clock_ticks, CPMU_GID_CLOCK_TICKS, BIT(0)),
> + /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdcurr, CPMU_GID_D2H_REQ, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdown, CPMU_GID_D2H_REQ, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdshared, CPMU_GID_D2H_REQ, BIT(3)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdany, CPMU_GID_D2H_REQ, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_rdownnodata, CPMU_GID_D2H_REQ, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_itomwr, CPMU_GID_D2H_REQ, BIT(6)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wrcurr, CPMU_GID_D2H_REQ, BIT(7)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_clflush, CPMU_GID_D2H_REQ, BIT(8)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cleanevict, CPMU_GID_D2H_REQ, BIT(9)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_dirtyevict, CPMU_GID_D2H_REQ, BIT(10)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cleanevictnodata, CPMU_GID_D2H_REQ, BIT(11)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wowrinv, CPMU_GID_D2H_REQ, BIT(12)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wowrinvf, CPMU_GID_D2H_REQ, BIT(13)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_wrinv, CPMU_GID_D2H_REQ, BIT(14)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_req_cacheflushed, CPMU_GID_D2H_REQ, BIT(16)),
> + /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspihiti, CPMU_GID_D2H_RSP, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspvhitv, CPMU_GID_D2H_RSP, BIT(6)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspihitse, CPMU_GID_D2H_RSP, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspshitse, CPMU_GID_D2H_RSP, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspsfwdm, CPMU_GID_D2H_RSP, BIT(7)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspifwdm, CPMU_GID_D2H_RSP, BIT(15)),
> + CPMU_PMU_EVENT_CXL_ATTR(d2h_rsp_rspvfwdv, CPMU_GID_D2H_RSP, BIT(22)),
> + /* CXL rev 3.0 Table 3-21 - CXL.cache - Mapping of H2D Requests to D2H Responses */
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpdata, CPMU_GID_H2D_REQ, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpinv, CPMU_GID_H2D_REQ, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_req_snpcur, CPMU_GID_H2D_REQ, BIT(3)),
> + /* CXL rev 3.0 Table 3-22 - H2D Response Opcode Encodings */
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_writepull, CPMU_GID_H2D_RSP, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_go, CPMU_GID_H2D_RSP, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_gowritepull, CPMU_GID_H2D_RSP, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_extcmp, CPMU_GID_H2D_RSP, BIT(6)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_gowritepulldrop, CPMU_GID_H2D_RSP, BIT(8)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_fastgowritepull, CPMU_GID_H2D_RSP, BIT(13)),
> + CPMU_PMU_EVENT_CXL_ATTR(h2d_rsp_goerrwritepull, CPMU_GID_H2D_RSP, BIT(15)),
> + /* CXL rev 3.0 Table 13-5 directly lists these */
> + CPMU_PMU_EVENT_CXL_ATTR(cachedata_d2h_data, CPMU_GID_CACHE_DATA, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(cachedata_h2d_data, CPMU_GID_CACHE_DATA, BIT(1)),
> + /* CXL rev 3.0 Table 3-29 M2S Req Memory Opcodes */
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_meminv, CPMU_GID_M2S_REQ, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrd, CPMU_GID_M2S_REQ, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrddata, CPMU_GID_M2S_REQ, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memrdfwd, CPMU_GID_M2S_REQ, BIT(3)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memwrfwd, CPMU_GID_M2S_REQ, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memspecrd, CPMU_GID_M2S_REQ, BIT(8)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_meminvnt, CPMU_GID_M2S_REQ, BIT(9)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_req_memcleanevict, CPMU_GID_M2S_REQ, BIT(10)),
> + /* CXL rev 3.0 Table 3-35 M2S RwD Memory Opcodes */
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_memwr, CPMU_GID_M2S_RWD, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_memwrptl, CPMU_GID_M2S_RWD, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_rwd_biconflict, CPMU_GID_M2S_RWD, BIT(4)),
> + /* CXL rev 3.0 Table 3-38 M2S BIRsp Memory Opcodes */
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_i, CPMU_GID_M2S_BIRSP, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_s, CPMU_GID_M2S_BIRSP, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_e, CPMU_GID_M2S_BIRSP, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_iblk, CPMU_GID_M2S_BIRSP, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_sblk, CPMU_GID_M2S_BIRSP, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(m2s_birsp_eblk, CPMU_GID_M2S_BIRSP, BIT(6)),
> + /* CXL rev 3.0 Table 3-40 S2M BISnp Opcodes */
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_cur, CPMU_GID_S2M_BISNP, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_data, CPMU_GID_S2M_BISNP, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_inv, CPMU_GID_S2M_BISNP, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_curblk, CPMU_GID_S2M_BISNP, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_datblk, CPMU_GID_S2M_BISNP, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_bisnp_invblk, CPMU_GID_S2M_BISNP, BIT(6)),
> + /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp, CPMU_GID_S2M_NDR, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps, CPMU_GID_S2M_NDR, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe, CPMU_GID_S2M_NDR, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack, CPMU_GID_S2M_NDR, BIT(3)),
> + /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_drs_memdata, CPMU_GID_S2M_DRS, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm, CPMU_GID_S2M_DRS, BIT(1)),
> + /* CXL rev 3.0 Table 13-5 directly lists these */
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_act, CPMU_GID_DDR, BIT(0)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_pre, CPMU_GID_DDR, BIT(1)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_casrd, CPMU_GID_DDR, BIT(2)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_caswr, CPMU_GID_DDR, BIT(3)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_refresh, CPMU_GID_DDR, BIT(4)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_selfrefreshent, CPMU_GID_DDR, BIT(5)),
> + CPMU_PMU_EVENT_CXL_ATTR(ddr_rfm, CPMU_GID_DDR, BIT(6)),
> + NULL
> +};
> +
> +static struct cpmu_event *cpmu_find_fixed_counter_event(struct cpmu_info *info,
> + int vid, int gid, int msk)
> +{
> + struct cpmu_event *cpmu_ev;
> +
> + list_for_each_entry(cpmu_ev, &info->events_fixed, node) {
> + if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
> + continue;
> +
> + /* Precise match for fixed counter */
> + if (msk == cpmu_ev->msk)
> + return cpmu_ev;
> + }
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static struct cpmu_event *cpmu_find_config_counter_event(struct cpmu_info *info,
> + int vid, int gid, int msk)
> +{
> + struct cpmu_event *cpmu_ev;
> +
> + list_for_each_entry(cpmu_ev, &info->events_configurable, node) {
> + if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
> + continue;
> +
> + /* Request mask must be subset of supported */
> + if (msk & ~cpmu_ev->msk)
> + continue;
> +
> + return cpmu_ev;
> + }
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static umode_t cpmu_event_is_visible(struct kobject *kobj, struct attribute *attr, int a)
> +{
> + struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr);
> + struct perf_pmu_events_attr *pmu_attr =
> + container_of(dev_attr, struct perf_pmu_events_attr, attr);
> + struct device *dev = kobj_to_dev(kobj);
> + struct cpmu_info *info = dev_get_drvdata(dev);
> + int vid = FIELD_GET(GENMASK_ULL(63, 48), pmu_attr->id);
> + int gid = FIELD_GET(GENMASK_ULL(47, 32), pmu_attr->id);
> + int msk = FIELD_GET(GENMASK_ULL(31, 0), pmu_attr->id);
> +
> + if (!IS_ERR(cpmu_find_fixed_counter_event(info, vid, gid, msk)))
> + return attr->mode;
> +
> + if (!IS_ERR(cpmu_find_config_counter_event(info, vid, gid, msk)))
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static const struct attribute_group cpmu_events = {
> + .name = "events",
> + .attrs = cpmu_event_attrs,
> + .is_visible = cpmu_event_is_visible,
> +};
> +
> +static ssize_t cpmu_format_sysfs_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct dev_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct dev_ext_attribute, attr);
> +
> + return sysfs_emit(buf, "%s\n", (char *)eattr->var);
> +}
> +
> +#define CPMU_FORMAT_ATTR(_name, _format)\
> + (&((struct dev_ext_attribute[]) { \
> + { \
> + .attr = __ATTR(_name, 0444, \
> + cpmu_format_sysfs_show, NULL), \
> + .var = (void *)_format \
> + } \
> + })[0].attr.attr)
> +
> +enum {
> + cpmu_mask_attr,
> + cpmu_gid_attr,
> + cpmu_vid_attr,
> + cpmu_threshold_attr,
> + cpmu_invert_attr,
> + cpmu_edge_attr,
> + cpmu_hdm_filter_en_attr,
> + cpmu_hdm_attr,
> +};
> +
> +static struct attribute *cpmu_format_attr[] = {
> + [cpmu_mask_attr] = CPMU_FORMAT_ATTR(mask, "config:0-31"),
> + [cpmu_gid_attr] = CPMU_FORMAT_ATTR(gid, "config:32-47"),
> + [cpmu_vid_attr] = CPMU_FORMAT_ATTR(vid, "config:48-63"),
> + [cpmu_threshold_attr] = CPMU_FORMAT_ATTR(threshold, "config1:0-15"),
> + [cpmu_invert_attr] = CPMU_FORMAT_ATTR(invert, "config1:16"),
> + [cpmu_edge_attr] = CPMU_FORMAT_ATTR(edge, "config1:17"),
> + [cpmu_hdm_filter_en_attr] = CPMU_FORMAT_ATTR(hdm_filter_en, "config1:18"),
> + [cpmu_hdm_attr] = CPMU_FORMAT_ATTR(hdm, "config2:0-15"),
> + NULL
> +};
> +
> +static umode_t cpmu_format_is_visible(struct kobject *kobj, struct attribute *attr, int a)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + /*
> + * Filter capability at the CPMU level, so hide the attributes if the particular
> + * filter is not supported.
> + */
> + if (attr == cpmu_format_attr[cpmu_hdm_filter_en_attr] ||
> + attr == cpmu_format_attr[cpmu_hdm_attr]) {
> + if (info->filter_hdm)
> + return 0444;
> + else
> + return 0;
> + } else {
> + return 0444;
> + }
> +}
> +
> +static const struct attribute_group cpmu_format_group = {
> + .name = "format",
> + .attrs = cpmu_format_attr,
> + .is_visible = cpmu_format_is_visible,
> +};
> +
> +static u32 cpmu_config_get_mask(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK_ULL(31, 0), event->attr.config);
> +}
> +
> +static u16 cpmu_config_get_gid(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK_ULL(47, 32), event->attr.config);
> +}
> +
> +static u16 cpmu_config_get_vid(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
> +}
> +
There should be at least two places which use GENMASK_ULL(63, 48), and
also git, mask. It's better to replace them by macros.
Ideally, we can use macros to replace all these magic numbers for the
format and define the macros close to cpmu_format_attr[]?
In case, we will change the bits for a format later. We will not miss
any places.
> +static u8 cpmu_config1_get_threshold(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK_ULL(15, 0), event->attr.config1);
> +}
> +
> +static bool cpmu_config1_get_invert(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(16), event->attr.config1);
> +}
> +
> +static bool cpmu_config1_get_edge(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(17), event->attr.config1);
> +}
> +
> +/*
> + * CPMU specification allows for 8 filters, each with a 16 bit value...
> + * So we need to find 8x16bits to store it in.
> + * As the value used for disable is 0xffff, a separate enable switch
> + * is needed.
> + */
> +
> +static bool cpmu_config1_hdm_filter_en(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(14), event->attr.config1);
> +}
> +
> +static u16 cpmu_config2_get_hdm_decoder(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(15, 0), event->attr.config2);
> +}
> +
> +static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + return cpumap_print_to_pagebuf(true, buf, cpumask_of(info->on_cpu));
> +}
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *cpmu_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL
> +};
> +
> +static const struct attribute_group cpmu_cpumask_group = {
> + .attrs = cpmu_cpumask_attrs,
> +};
> +
> +static const struct attribute_group *cpmu_attr_groups[] = {
> + &cpmu_events,
> + &cpmu_format_group,
> + &cpmu_cpumask_group,
> + NULL
> +};
> +
> +/* If counter_idx == NULL, don't try to allocate a counter. */
> +static int cpmu_get_event_idx(struct perf_event *event, int *counter_idx, int *event_idx)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + DECLARE_BITMAP(configurable_and_free, CPMU_MAX_COUNTERS);
> + struct cpmu_event *cpmu_ev;
> + u32 mask;
> + u16 gid, vid;
> + int i;
> +
> + vid = cpmu_config_get_vid(event);
> + gid = cpmu_config_get_gid(event);
> + mask = cpmu_config_get_mask(event);
> +
> + cpmu_ev = cpmu_find_fixed_counter_event(info, vid, gid, mask);
> + if (!IS_ERR(cpmu_ev)) {
> + if (!counter_idx)
> + return 0;
> + if (!info->hw_events[cpmu_ev->counter_idx]) {
Use info->used_counter_bm?
> + *counter_idx = cpmu_ev->counter_idx;
> + return 0;
> + }
> + /* Fixed counter is in use, but maybe a configurable one? */
> + }
> +
> + cpmu_ev = cpmu_find_config_counter_event(info, vid, gid, mask);
> + if (!IS_ERR(cpmu_ev)) {
> + if (!counter_idx)
> + return 0;
> +
> + bitmap_andnot(configurable_and_free, info->conf_counter_bm,
> + info->used_counter_bm, CPMU_MAX_COUNTERS);
> +
> + i = find_first_bit(configurable_and_free, CPMU_MAX_COUNTERS);
> + if (i == CPMU_MAX_COUNTERS)
> + return -EINVAL;
> +
> + *counter_idx = i;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int cpmu_event_init(struct perf_event *event)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> +
> + event->cpu = info->on_cpu;
> + /* Top level type sanity check - is this a Hardware Event being requested */
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> + return -EOPNOTSUPP;
> + /* TODO: Validation of any filter */
> +
> + /*
> + * Verify that it is possible to count what was requested. Either must
> + * be a fixed counter that is a precise match or a configurable counter
> + * where this is a subset.
> + */
> + return cpmu_get_event_idx(event, NULL, NULL);
> +}
> +
> +static void cpmu_pmu_enable(struct pmu *pmu)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(pmu);
> + void __iomem *base = info->base;
> +
> + /* We don't have a global enable, but we 'might' have a global freeze which we can use */
> + if (info->freeze_for_enable) {
> + /* Can assume frozen at this stage */
> + writeq(0, base + CPMU_FREEZE_REG);
> +
> + return;
> + }
> +}
> +
> +static void cpmu_pmu_disable(struct pmu *pmu)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(pmu);
> + void __iomem *base = info->base;
> +
> + if (info->freeze_for_enable) {
> + /*
> + * Whilst bits above number of counters are RsvdZ
> + * they are unlikely to be repurposed given
> + * number of counters is allowed to be 64 leaving
> + * no reserved bits. Hence this is only slightly
> + * naughty.
> + */
> + writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
> + return;
> + }
> +}
> +
> +static void cpmu_event_start(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + void __iomem *base = info->base;
> + u64 cfg, prev_cnt;
> +
> + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
> + return;
> +
> + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
> + hwc->state = 0;
> +
> + /*
> + * Currently only hdm filter control is implemnted, this code will
> + * want generalizing when more filters are added.
> + */
> + if (info->filter_hdm) {
> + if (cpmu_config1_hdm_filter_en(event))
> + cfg = cpmu_config2_get_hdm_decoder(event);
> + else
> + cfg = GENMASK(15, 0);
> + writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
> + }
> +
> + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
> +
> + /* Fixed purpose counters have next two fields RO */
> + if (test_bit(hwc->idx, info->conf_counter_bm)) {
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
> + }
> + cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
> + /*
> + * For events that generate only 1 count per clock the CXL 3.0 spec
> + * states the threshold shall be set to 1 but if set to 0 it will
> + * count the raw value anwyay?
> + * There is no definition of what events will count multiple per cycle
> + * and hence to which non 1 values of threshold can apply.
> + * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
> + */
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
> + cpmu_config1_get_threshold(event));
> + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> +
> + local64_set(&hwc->prev_count, 0);
> + writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
> +
> + if (flags & PERF_EF_RELOAD) {
> + prev_cnt = local64_read(&hwc->prev_count);
> + writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
> + }
The hwc->prev_count is already unconditionally set to 0.
> +
> + perf_event_update_userpage(event);
> +}
> +
> +static u64 cpmu_read_counter(struct perf_event *event)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + void __iomem *base = info->base;
> +
> + return readq(base + CPMU_COUNTER_REG(event->hw.idx));
> +}
> +
> +static void __cpmu_read(struct perf_event *event, bool overflow)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + u64 new_cnt, prev_cnt, delta;
> +
> + do {
> + prev_cnt = local64_read(&hwc->prev_count);
> + new_cnt = cpmu_read_counter(event);
> + } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
> +
> + /*
> + * If we know an overflow occur then take that into account.
> + * Note counter is not reset as that would lose events
> + */
> + delta = (new_cnt - prev_cnt) & GENMASK(info->counter_width - 1, 0);
> + if (overflow && delta < GENMASK(info->counter_width - 1, 0))
> + delta += (1UL << info->counter_width);
> +
> + local64_add(delta, &event->count);
> +}
> +
> +static void cpmu_read(struct perf_event *event)
> +{
> + __cpmu_read(event, false);
> +}
> +
> +static void cpmu_event_stop(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + void __iomem *base = info->base;
> + struct hw_perf_event *hwc = &event->hw;
> + u64 cfg;
> +
> + cpmu_read(event);
> + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
> + hwc->state |= PERF_HES_STOPPED;
> +
> + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> + cfg &= ~(FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1) |
> + FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1));
> + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> +
> + if (hwc->state & PERF_HES_UPTODATE)
> + return;
The PERF_HES_UPTODATE is used to update the event count if there is a
request and the !(hwc->state & PERF_HES_UPTODATE). It can avoid a read
if no PERF_HES_UPTODATE is requested.
Since the read is invoked unconditionally above, I guess you don't need
the check.
Thanks,
Kan
> +
> + hwc->state |= PERF_HES_UPTODATE;
> +}
> +
> +/*
> + * Reset ensures no possibility of any information leaking to wrong
> + * counter. Note that all fields written during start()
> + */
> +static void cpmu_reset_counter(struct cpmu_info *info, int idx)
> +{
> + void __iomem *base = info->base;
> +
> + /* Much of this register is read only */
> + writeq(0, base + CPMU_EVENT_CAP_REG(idx));
> + /* Filters are not per counter, so no reset here */
> + writeq(0, base + CPMU_COUNTER_REG(idx));
> +}
> +
> +static int cpmu_event_add(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int idx, rc;
> + int event_idx = 0;
> +
> + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
> +
> + rc = cpmu_get_event_idx(event, &idx, &event_idx);
> + if (rc < 0)
> + return rc;
> +
> + hwc->idx = idx;
> +
> + /* Only set for configurable counters */
> + hwc->event_base = event_idx;
> + info->hw_events[idx] = event;
> + set_bit(idx, info->used_counter_bm);
> +
> + cpmu_reset_counter(info, idx);
> +
> + if (flags & PERF_EF_START)
> + cpmu_event_start(event, PERF_EF_RELOAD);
> +
> + return 0;
> +}
> +
> +static void cpmu_event_del(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> +
> + cpmu_event_stop(event, PERF_EF_UPDATE);
> + clear_bit(hwc->idx, info->used_counter_bm);
> + info->hw_events[hwc->idx] = NULL;
> + perf_event_update_userpage(event);
> +}
> +
> +static irqreturn_t cpmu_irq(int irq, void *data)
> +{
> + struct cpmu_info *info = data;
> + void __iomem *base = info->base;
> + u64 overflowed;
> + DECLARE_BITMAP(overflowedbm, 64);
> + int i;
> +
> + overflowed = readq(base + CPMU_OVERFLOW_REG);
> +
> + /* Interrupt may be shared, so maybe it isn't ours */
> + if (!overflowed)
> + return IRQ_NONE;
> +
> + bitmap_from_arr64(overflowedbm, &overflowed, 64);
> + for_each_set_bit(i, overflowedbm, info->num_counters) {
> + struct perf_event *event = info->hw_events[i];
> +
> + if (!event) {
> + dev_dbg(info->pmu.dev,
> + "overflow but on non enabled counter %d\n", i);
> + continue;
> + }
> +
> + __cpmu_read(event, true);
> + }
> +
> + writeq(overflowed, base + CPMU_OVERFLOW_REG);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int cxl_cpmu_probe(struct device *dev)
> +{
> + struct cxl_cpmu *cpmu = to_cxl_cpmu(dev);
> + struct pci_dev *pdev = to_pci_dev(dev->parent);
> + struct cpmu_info *info;
> + char *irq_name;
> + int rc, irq;
> +
> + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> + if (!info)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&info->events_fixed);
> + INIT_LIST_HEAD(&info->events_configurable);
> +
> + info->base = cpmu->base;
> +
> + info->on_cpu = -1;
> + rc = cpmu_parse_caps(dev, info);
> + if (rc)
> + return rc;
> +
> + info->hw_events = devm_kcalloc(dev, sizeof(*info->hw_events),
> + info->num_counters, GFP_KERNEL);
> + if (!info->hw_events)
> + return -ENOMEM;
> +
> + info->pmu = (struct pmu) {
> + .name = dev_name(dev),
> + .parent = dev,
> + .module = THIS_MODULE,
> + .event_init = cpmu_event_init,
> + .pmu_enable = cpmu_pmu_enable,
> + .pmu_disable = cpmu_pmu_disable,
> + .add = cpmu_event_add,
> + .del = cpmu_event_del,
> + .start = cpmu_event_start,
> + .stop = cpmu_event_stop,
> + .read = cpmu_read,
> + .task_ctx_nr = perf_invalid_context,
> + .attr_groups = cpmu_attr_groups,
> + .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
> + };
> +
> + if (info->irq <= 0)
> + return -EINVAL;
> +
> + rc = pci_irq_vector(pdev, info->irq);
> + if (rc < 0)
> + return rc;
> + irq = rc;
> +
> + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_overflow\n", dev_name(dev));
> + if (!irq_name)
> + return -ENOMEM;
> +
> + rc = devm_request_irq(dev, irq, cpmu_irq, IRQF_SHARED, irq_name, info);
> + if (rc)
> + return rc;
> + info->irq = irq;
> +
> + rc = cpuhp_state_add_instance(cpmu_cpuhp_state_num, &info->node);
> + if (rc)
> + return rc;
> +
> + rc = perf_pmu_register(&info->pmu, info->pmu.name, -1);
> + if (rc)
> + return rc;
> +
> + dev_set_drvdata(dev, info);
> +
> + return 0;
> +}
> +
> +static void cxl_cpmu_remove(struct device *dev)
> +{
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + perf_pmu_unregister(&info->pmu);
> + cpuhp_state_remove_instance_nocalls(cpmu_cpuhp_state_num, &info->node);
> +}
> +
> +static struct cxl_driver cxl_cpmu_driver = {
> + .name = "cxl_cpmu",
> + .probe = cxl_cpmu_probe,
> + .remove = cxl_cpmu_remove,
> + .id = CXL_DEVICE_CPMU,
> +};
> +
> +static int cpmu_online_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
> +
> + if (info->on_cpu != -1)
> + return 0;
> +
> + info->on_cpu = cpu;
> + WARN_ON(irq_set_affinity(info->irq, cpumask_of(cpu)));
> +
> + return 0;
> +}
> +
> +static int cpmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
> + unsigned int target;
> +
> + if (info->on_cpu != cpu)
> + return 0;
> +
> + info->on_cpu = -1;
> + target = cpumask_first(cpu_online_mask);
> + if (target >= nr_cpu_ids) {
> + dev_err(info->pmu.dev, "Unable to find a suitable CPU\n");
> + return 0;
> + }
> +
> + perf_pmu_migrate_context(&info->pmu, cpu, target);
> + info->on_cpu = target;
> + WARN_ON(irq_set_affinity(info->irq, cpumask_of(target)));
> +
> + return 0;
> +}
> +
> +static __init int cxl_cpmu_init(void)
> +{
> + int rc;
> +
> + rc = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "AP_PERF_CPMU_ONLINE",
> + cpmu_online_cpu, cpmu_offline_cpu);
> + if (rc < 0)
> + return rc;
> + cpmu_cpuhp_state_num = rc;
> +
> + rc = cxl_driver_register(&cxl_cpmu_driver);
> + if (rc)
> + cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
> +
> + return rc;
> +}
> +
> +static __exit void cxl_cpmu_exit(void)
> +{
> + cxl_driver_unregister(&cxl_cpmu_driver);
> + cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
> +}
> +
> +MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS(CXL);
> +module_init(cxl_cpmu_init);
> +module_exit(cxl_cpmu_exit);
> +MODULE_ALIAS_CXL(CXL_DEVICE_CPMU);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-27 17:04 ` Liang, Kan
@ 2023-03-28 10:54 ` Jonathan Cameron
2023-03-28 11:01 ` Greg KH
0 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-28 10:54 UTC (permalink / raw)
To: Liang, Kan
Cc: linux-cxl, peterz, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang, gregkh
On Mon, 27 Mar 2023 13:04:08 -0400
"Liang, Kan" <kan.liang@linux.intel.com> wrote:
> On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> > Some PMUs have well defined parents such as PCI devices.
> > As the device_initialize() and device_add() are all within
> > pmu_dev_alloc() which is called from perf_pmu_register()
> > there is no opportunity to set the parent from within a driver.
> >
> > Add a struct device *parent field to struct pmu and use that
> > to set the parent.
>
> Why we want a PMU parent? Maybe I missed it. I don't see that the parent
> is used anywhere.
This allows you to identify the association between PMU and the hardware related
device that is providing it by looking at the directory structure in sysfs rather
than putting them directly under /sys/devices.
ls -l /sys/bus/event_sources/devices/
... armv8_pmuv3_0 -> ../../../devices/arm8_pmuv3_0
... breakpoint -> ../../../devices/breakpoint
... cpmu0 -> ../../../devices/pci0000:0c/0000:0c:00.0/0000:0d:00.0/cpmu0/cpmu0
etc
(the first cpmu0 is the parent registered as a child of the PCI EP and used for
driver binding). So it's of use to userspace rather than in the kernel driver
itself.
Note that almost nothing is normally in the top level /sys/devices other than
event_sources - because nearly all other struct device instances created by
subsystems have parents assigned.
On my system
ls /sys/devices
armv8_pmuv3_0 LNXSYSTEM:00 pci0000:0c pnp0 system uprobe
breakpoint pci0000:00 platform software tracepoint virtual
+CC Greg KH for input on whether / why this make sense.
Thanks,
Jonathan
>
> Thanks,
> Kan
>
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> > include/linux/perf_event.h | 1 +
> > kernel/events/core.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> > index d5628a7b5eaa..b99db1eda72c 100644
> > --- a/include/linux/perf_event.h
> > +++ b/include/linux/perf_event.h
> > @@ -303,6 +303,7 @@ struct pmu {
> >
> > struct module *module;
> > struct device *dev;
> > + struct device *parent;
> > const struct attribute_group **attr_groups;
> > const struct attribute_group **attr_update;
> > const char *name;
> > diff --git a/kernel/events/core.c b/kernel/events/core.c
> > index fb3e436bcd4a..a84c282221f2 100644
> > --- a/kernel/events/core.c
> > +++ b/kernel/events/core.c
> > @@ -11367,6 +11367,7 @@ static int pmu_dev_alloc(struct pmu *pmu)
> >
> > dev_set_drvdata(pmu->dev, pmu);
> > pmu->dev->bus = &pmu_bus;
> > + pmu->dev->parent = pmu->parent;
> > pmu->dev->release = pmu_dev_release;
> >
> > ret = dev_set_name(pmu->dev, "%s", pmu->name);
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-28 10:54 ` Jonathan Cameron
@ 2023-03-28 11:01 ` Greg KH
2023-03-29 8:55 ` Jonathan Cameron
0 siblings, 1 reply; 20+ messages in thread
From: Greg KH @ 2023-03-28 11:01 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Liang, Kan, linux-cxl, peterz, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
On Tue, Mar 28, 2023 at 11:54:44AM +0100, Jonathan Cameron wrote:
> On Mon, 27 Mar 2023 13:04:08 -0400
> "Liang, Kan" <kan.liang@linux.intel.com> wrote:
>
> > On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> > > Some PMUs have well defined parents such as PCI devices.
> > > As the device_initialize() and device_add() are all within
> > > pmu_dev_alloc() which is called from perf_pmu_register()
> > > there is no opportunity to set the parent from within a driver.
> > >
> > > Add a struct device *parent field to struct pmu and use that
> > > to set the parent.
> >
> > Why we want a PMU parent? Maybe I missed it. I don't see that the parent
> > is used anywhere.
>
> This allows you to identify the association between PMU and the hardware related
> device that is providing it by looking at the directory structure in sysfs rather
> than putting them directly under /sys/devices.
>
> ls -l /sys/bus/event_sources/devices/
>
> ... armv8_pmuv3_0 -> ../../../devices/arm8_pmuv3_0
> ... breakpoint -> ../../../devices/breakpoint
> ... cpmu0 -> ../../../devices/pci0000:0c/0000:0c:00.0/0000:0d:00.0/cpmu0/cpmu0
> etc
>
> (the first cpmu0 is the parent registered as a child of the PCI EP and used for
> driver binding). So it's of use to userspace rather than in the kernel driver
> itself.
>
> Note that almost nothing is normally in the top level /sys/devices other than
> event_sources - because nearly all other struct device instances created by
> subsystems have parents assigned.
>
> On my system
>
> ls /sys/devices
>
> armv8_pmuv3_0 LNXSYSTEM:00 pci0000:0c pnp0 system uprobe
> breakpoint pci0000:00 platform software tracepoint virtual
>
> +CC Greg KH for input on whether / why this make sense.
That doesn't make sense, nothing should be in /sys/devices/ EXCEPT the
root device of busses. Everything else is wrong and should have their
code fixed up (i.e. "breakpoint", "software", etc.)
thanks,
greg k-h
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-28 11:01 ` Greg KH
@ 2023-03-29 8:55 ` Jonathan Cameron
2023-03-29 9:03 ` Greg KH
0 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-29 8:55 UTC (permalink / raw)
To: Greg KH
Cc: Liang, Kan, linux-cxl, peterz, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
On Tue, 28 Mar 2023 13:01:08 +0200
Greg KH <gregkh@linuxfoundation.org> wrote:
> On Tue, Mar 28, 2023 at 11:54:44AM +0100, Jonathan Cameron wrote:
> > On Mon, 27 Mar 2023 13:04:08 -0400
> > "Liang, Kan" <kan.liang@linux.intel.com> wrote:
> >
> > > On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> > > > Some PMUs have well defined parents such as PCI devices.
> > > > As the device_initialize() and device_add() are all within
> > > > pmu_dev_alloc() which is called from perf_pmu_register()
> > > > there is no opportunity to set the parent from within a driver.
> > > >
> > > > Add a struct device *parent field to struct pmu and use that
> > > > to set the parent.
> > >
> > > Why we want a PMU parent? Maybe I missed it. I don't see that the parent
> > > is used anywhere.
> >
> > This allows you to identify the association between PMU and the hardware related
> > device that is providing it by looking at the directory structure in sysfs rather
> > than putting them directly under /sys/devices.
> >
> > ls -l /sys/bus/event_sources/devices/
> >
> > ... armv8_pmuv3_0 -> ../../../devices/arm8_pmuv3_0
> > ... breakpoint -> ../../../devices/breakpoint
> > ... cpmu0 -> ../../../devices/pci0000:0c/0000:0c:00.0/0000:0d:00.0/cpmu0/cpmu0
> > etc
> >
> > (the first cpmu0 is the parent registered as a child of the PCI EP and used for
> > driver binding). So it's of use to userspace rather than in the kernel driver
> > itself.
> >
> > Note that almost nothing is normally in the top level /sys/devices other than
> > event_sources - because nearly all other struct device instances created by
> > subsystems have parents assigned.
> >
> > On my system
> >
> > ls /sys/devices
> >
> > armv8_pmuv3_0 LNXSYSTEM:00 pci0000:0c pnp0 system uprobe
> > breakpoint pci0000:00 platform software tracepoint virtual
> >
> > +CC Greg KH for input on whether / why this make sense.
>
> That doesn't make sense, nothing should be in /sys/devices/ EXCEPT the
> root device of busses. Everything else is wrong and should have their
> code fixed up (i.e. "breakpoint", "software", etc.)
Thanks Greg.
I was thinking to cycle back round to that once I'd got agreement on 'some' devices,
but great to have clarity from the start that these should all have
parents.
For a few cases the parent is not immediately obvious but we'll figure it out.
Jonathan
>
> thanks,
>
> greg k-h
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/5] perf: Allow a PMU to have a parent.
2023-03-29 8:55 ` Jonathan Cameron
@ 2023-03-29 9:03 ` Greg KH
0 siblings, 0 replies; 20+ messages in thread
From: Greg KH @ 2023-03-29 9:03 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Liang, Kan, linux-cxl, peterz, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
On Wed, Mar 29, 2023 at 09:55:04AM +0100, Jonathan Cameron wrote:
> On Tue, 28 Mar 2023 13:01:08 +0200
> Greg KH <gregkh@linuxfoundation.org> wrote:
>
> > On Tue, Mar 28, 2023 at 11:54:44AM +0100, Jonathan Cameron wrote:
> > > On Mon, 27 Mar 2023 13:04:08 -0400
> > > "Liang, Kan" <kan.liang@linux.intel.com> wrote:
> > >
> > > > On 2023-03-24 1:13 p.m., Jonathan Cameron wrote:
> > > > > Some PMUs have well defined parents such as PCI devices.
> > > > > As the device_initialize() and device_add() are all within
> > > > > pmu_dev_alloc() which is called from perf_pmu_register()
> > > > > there is no opportunity to set the parent from within a driver.
> > > > >
> > > > > Add a struct device *parent field to struct pmu and use that
> > > > > to set the parent.
> > > >
> > > > Why we want a PMU parent? Maybe I missed it. I don't see that the parent
> > > > is used anywhere.
> > >
> > > This allows you to identify the association between PMU and the hardware related
> > > device that is providing it by looking at the directory structure in sysfs rather
> > > than putting them directly under /sys/devices.
> > >
> > > ls -l /sys/bus/event_sources/devices/
> > >
> > > ... armv8_pmuv3_0 -> ../../../devices/arm8_pmuv3_0
> > > ... breakpoint -> ../../../devices/breakpoint
> > > ... cpmu0 -> ../../../devices/pci0000:0c/0000:0c:00.0/0000:0d:00.0/cpmu0/cpmu0
> > > etc
> > >
> > > (the first cpmu0 is the parent registered as a child of the PCI EP and used for
> > > driver binding). So it's of use to userspace rather than in the kernel driver
> > > itself.
> > >
> > > Note that almost nothing is normally in the top level /sys/devices other than
> > > event_sources - because nearly all other struct device instances created by
> > > subsystems have parents assigned.
> > >
> > > On my system
> > >
> > > ls /sys/devices
> > >
> > > armv8_pmuv3_0 LNXSYSTEM:00 pci0000:0c pnp0 system uprobe
> > > breakpoint pci0000:00 platform software tracepoint virtual
> > >
> > > +CC Greg KH for input on whether / why this make sense.
> >
> > That doesn't make sense, nothing should be in /sys/devices/ EXCEPT the
> > root device of busses. Everything else is wrong and should have their
> > code fixed up (i.e. "breakpoint", "software", etc.)
>
> Thanks Greg.
>
> I was thinking to cycle back round to that once I'd got agreement on 'some' devices,
> but great to have clarity from the start that these should all have
> parents.
>
> For a few cases the parent is not immediately obvious but we'll figure it out.
If there is no "real" parent, then it is a virtual device and belongs
under the "virtual" directory. Otherwise why are these "devices" at all
with such generic names?
thanks,
greg k-h
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver
2023-03-27 17:07 ` Liang, Kan
@ 2023-03-29 13:11 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2023-03-29 13:11 UTC (permalink / raw)
To: Liang, Kan
Cc: linux-cxl, peterz, mingo, acme, mark.rutland, will,
dan.j.williams, linuxarm, linux-perf-users, linux-kernel,
Davidlohr Bueso, Dave Jiang
Hi Kan,
Thanks for another quick review.
A few comments on how I responded to feedback inline, but in short
I accepted all of it and made the obvious changes.
> > +static u16 cpmu_config_get_vid(struct perf_event *event)
> > +{
> > + return FIELD_GET(GENMASK_ULL(63, 48), event->attr.config);
> > +}
> > +
>
> There should be at least two places which use GENMASK_ULL(63, 48), and
> also git, mask. It's better to replace them by macros.
>
> Ideally, we can use macros to replace all these magic numbers for the
> format and define the macros close to cpmu_format_attr[]?
> In case, we will change the bits for a format later. We will not miss
> any places.
>
Good idea and lo and behold one of them was mismatched.
(Filter enable was described as bit 18 of config1 but bit 14 was read).
...
> > +static const struct attribute_group *cpmu_attr_groups[] = {
> > + &cpmu_events,
> > + &cpmu_format_group,
> > + &cpmu_cpumask_group,
> > + NULL
> > +};
> > +
> > +/* If counter_idx == NULL, don't try to allocate a counter. */
> > +static int cpmu_get_event_idx(struct perf_event *event, int *counter_idx, int *event_idx)
> > +{
> > + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> > + DECLARE_BITMAP(configurable_and_free, CPMU_MAX_COUNTERS);
> > + struct cpmu_event *cpmu_ev;
> > + u32 mask;
> > + u16 gid, vid;
> > + int i;
> > +
> > + vid = cpmu_config_get_vid(event);
> > + gid = cpmu_config_get_gid(event);
> > + mask = cpmu_config_get_mask(event);
> > +
> > + cpmu_ev = cpmu_find_fixed_counter_event(info, vid, gid, mask);
> > + if (!IS_ERR(cpmu_ev)) {
> > + if (!counter_idx)
> > + return 0;
> > + if (!info->hw_events[cpmu_ev->counter_idx]) {
>
> Use info->used_counter_bm?
I guess that's more obviously similar with the handling below and possibly
a small performance saving, so sure.
>
> > + *counter_idx = cpmu_ev->counter_idx;
> > + return 0;
> > + }
> > + /* Fixed counter is in use, but maybe a configurable one? */
> > + }
> > +
> > + cpmu_ev = cpmu_find_config_counter_event(info, vid, gid, mask);
> > + if (!IS_ERR(cpmu_ev)) {
> > + if (!counter_idx)
> > + return 0;
> > +
> > + bitmap_andnot(configurable_and_free, info->conf_counter_bm,
> > + info->used_counter_bm, CPMU_MAX_COUNTERS);
> > +
> > + i = find_first_bit(configurable_and_free, CPMU_MAX_COUNTERS);
> > + if (i == CPMU_MAX_COUNTERS)
> > + return -EINVAL;
> > +
> > + *counter_idx = i;
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
...
> > +static void cpmu_event_start(struct perf_event *event, int flags)
> > +{
> > + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> > + struct hw_perf_event *hwc = &event->hw;
> > + void __iomem *base = info->base;
> > + u64 cfg, prev_cnt;
> > +
> > + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
> > + return;
> > +
> > + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
> > + hwc->state = 0;
> > +
> > + /*
> > + * Currently only hdm filter control is implemnted, this code will
> > + * want generalizing when more filters are added.
> > + */
> > + if (info->filter_hdm) {
> > + if (cpmu_config1_hdm_filter_en(event))
> > + cfg = cpmu_config2_get_hdm_decoder(event);
> > + else
> > + cfg = GENMASK(15, 0);
> > + writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
> > + }
> > +
> > + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
> > +
> > + /* Fixed purpose counters have next two fields RO */
> > + if (test_bit(hwc->idx, info->conf_counter_bm)) {
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, hwc->event_base);
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
> > + }
> > + cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
> > + /*
> > + * For events that generate only 1 count per clock the CXL 3.0 spec
> > + * states the threshold shall be set to 1 but if set to 0 it will
> > + * count the raw value anwyay?
> > + * There is no definition of what events will count multiple per cycle
> > + * and hence to which non 1 values of threshold can apply.
> > + * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
> > + */
> > + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
> > + cpmu_config1_get_threshold(event));
> > + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> > +
> > + local64_set(&hwc->prev_count, 0);
> > + writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
> > +
> > + if (flags & PERF_EF_RELOAD) {
> > + prev_cnt = local64_read(&hwc->prev_count);
> > + writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
> > + }
>
> The hwc->prev_count is already unconditionally set to 0.
Good spot. This driver has been evolving for too long so I'm missing
silly thing like this. I'll drop the PERF_EF_RELOAD handling as
it doesn't do anything useful and it seems to be a bit random
if uncore drivers have support or not.
>
> > +
> > + perf_event_update_userpage(event);
> > +}
...
> > +static void cpmu_event_stop(struct perf_event *event, int flags)
> > +{
> > + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> > + void __iomem *base = info->base;
> > + struct hw_perf_event *hwc = &event->hw;
> > + u64 cfg;
> > +
> > + cpmu_read(event);
> > + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
> > + hwc->state |= PERF_HES_STOPPED;
> > +
> > + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> > + cfg &= ~(FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1) |
> > + FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1));
> > + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> > +
> > + if (hwc->state & PERF_HES_UPTODATE)
> > + return;
>
> The PERF_HES_UPTODATE is used to update the event count if there is a
> request and the !(hwc->state & PERF_HES_UPTODATE). It can avoid a read
> if no PERF_HES_UPTODATE is requested.
> Since the read is invoked unconditionally above, I guess you don't need
> the check.
Dropped. Even looking very locally we set the bit on the next line anyway
and setting an already set bit is harmless.
>
> Thanks,
> Kan
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-03-29 13:11 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-24 17:13 [PATCH v2 0/5] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 1/5] cxl: Add function to count regblocks of a given type Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 2/5] perf: Allow a PMU to have a parent Jonathan Cameron
2023-03-27 17:04 ` Liang, Kan
2023-03-28 10:54 ` Jonathan Cameron
2023-03-28 11:01 ` Greg KH
2023-03-29 8:55 ` Jonathan Cameron
2023-03-29 9:03 ` Greg KH
2023-03-24 17:13 ` [PATCH v2 3/5] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2023-03-24 21:01 ` kernel test robot
2023-03-27 15:50 ` Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 4/5] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2023-03-24 21:12 ` kernel test robot
2023-03-27 15:50 ` Jonathan Cameron
2023-03-24 21:42 ` kernel test robot
2023-03-24 22:03 ` kernel test robot
2023-03-24 22:03 ` kernel test robot
2023-03-27 17:07 ` Liang, Kan
2023-03-29 13:11 ` Jonathan Cameron
2023-03-24 17:13 ` [PATCH v2 5/5] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
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