From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Garry Subject: Re: [PATCH] perf vendor events arm64: Enable JSON events for eMAG Date: Fri, 3 Aug 2018 15:41:06 +0100 Message-ID: References: <20180803041811.17065-1-seanvk.dev@oregontracks.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180803041811.17065-1-seanvk.dev@oregontracks.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Sean V Kelley , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: skelley@amperecomputing.com, Peter Zijlstra , Will Deacon , Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , Ganapatrao Kulkarni , Namhyung Kim , William Cohen , Jiri Olsa List-Id: linux-perf-users.vger.kernel.org On 03/08/2018 05:18, Sean V Kelley wrote: > This patch adds the Ampere Computing eMAG file. This platform > follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where > applicable. > > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: John Garry > Cc: Will Deacon > Cc: Ganapatrao Kulkarni > Cc: William Cohen > > Signed-off-by: Sean V Kelley Reviewed-by: John Garry > --- > .../arch/arm64/ampere/emag/core-imp-def.json | 32 +++++++++++++++++++ > tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > 2 files changed, 33 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json > > diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json > new file mode 100644 > index 000000000000..bc03c06c3918 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json > @@ -0,0 +1,32 @@ > +[ > + { > + "ArchStdEvent": "L1D_CACHE_RD", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_WR", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_RD", > + }, > + { > + "ArchStdEvent": "L1D_CACHE_REFILL_WR", > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL_RD", > + }, > + { > + "ArchStdEvent": "L1D_TLB_REFILL_WR", > + }, > + { > + "ArchStdEvent": "L1D_TLB_RD", > + }, > + { > + "ArchStdEvent": "L1D_TLB_WR", > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_RD", > + }, > + { > + "ArchStdEvent": "BUS_ACCESS_WR", > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index f03e26ecb658..59cd8604b0bd 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -16,3 +16,4 @@ > 0x00000000420f5160,v1,cavium/thunderx2,core > 0x00000000430f0af0,v1,cavium/thunderx2,core > 0x00000000480fd010,v1,hisilicon/hip08,core > +0x00000000500f0000,v1,ampere/emag,core We could order by vendor/platform, but not so important as I see. >