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d="asc'?scan'208";a="145160516" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Apr 2023 23:24:23 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 2 Apr 2023 23:24:23 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Sun, 2 Apr 2023 23:24:20 -0700 Date: Mon, 3 Apr 2023 07:24:06 +0100 From: Conor Dooley To: Changhuang Liang CC: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Jack Zhu , , , , Subject: Re: [PATCH v2 2/3] phy: starfive: Add mipi dphy rx support Message-ID: <0dd5e35b-512e-41ed-af33-f94b7e2868c1@spud> References: <20230223015952.201841-1-changhuang.liang@starfivetech.com> <20230223015952.201841-3-changhuang.liang@starfivetech.com> <2aa1bdbd-e37e-941a-9422-0908545c14f7@starfivetech.com> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230402_232427_908594_ACFB45F7 X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============2563540612157938343==" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org --===============2563540612157938343== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="H+2gs+RwcKc2bDgt" Content-Disposition: inline --H+2gs+RwcKc2bDgt Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Apr 03, 2023 at 09:39:00AM +0800, Changhuang Liang wrote: > On 2023/3/31 21:52, Vinod Koul wrote: > > On 21-03-23, 14:08, Changhuang Liang wrote: > >> On 2023/3/20 20:37, Vinod Koul wrote: > >>> On 22-02-23, 17:59, Changhuang Liang wrote: > >>>> [...] > >>>> +static const struct regval_t stf_dphy_init_list[] =3D { > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(4), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(8), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(12), 0x0000fff0 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(16), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(20), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(24), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(28), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(32), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(36), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(48), 0x24000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(52), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(56), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(60), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(64), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(68), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(72), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(76), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(80), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(84), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(88), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(92), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(96), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(100), 0x02000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(104), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(108), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(112), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(116), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(120), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(124), 0x0000000c }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(128), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(132), 0xcc500000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(136), 0x000000cc }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(140), 0x00000000 }, > >>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(144), 0x00000000 }, > >>>> +}; > >>>> + > >>>> +static int stf_dphy_configure(struct phy *phy, union phy_configure_= opts *opts) > >>>> +{ > >>>> + struct stf_dphy *dphy =3D phy_get_drvdata(phy); > >>>> + int map[6] =3D {4, 0, 1, 2, 3, 5}; > >>> > >>> what does this mean? > >> > >> This is the physical lane and logical lane mapping table, should I add= a note for it? > >=20 > > Yes please. Also will the mapping be always static or ever change? > > =20 >=20 > The mapping is always static on the visionfive2 single board computer. > Thanks for your comments. What about other boards featuring a JH7110? --H+2gs+RwcKc2bDgt Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZCpw9gAKCRB4tDGHoIJi 0j48AP93KM8qo+2qFu0Q08mVxv8JhhX9LTXYPZrZ5Cr2SB5nbwEAwF35RRfom50o FPXKuMztozN4Mw3e3uMacj/9cRNOlAo= =1C53 -----END PGP SIGNATURE----- --H+2gs+RwcKc2bDgt-- --===============2563540612157938343== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy --===============2563540612157938343==--