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* [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes
@ 2023-03-31 15:12 Dmitry Baryshkov
  2023-03-31 15:12 ` [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl Dmitry Baryshkov
  2023-04-10 15:18 ` [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Vinod Koul
  0 siblings, 2 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2023-03-31 15:12 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold, stable

All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of
lanes to 2.

Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support")
Cc: stable@vger.kernel.org # 5.15
Sgned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b1e81530d551..f378c1ebefd7 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2331,7 +2331,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
 };
 
 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-	.lanes			= 1,
+	.lanes			= 2,
 
 	.tbls = {
 		.serdes		= sc8180x_qmp_pcie_serdes_tbl,
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl
  2023-03-31 15:12 [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Dmitry Baryshkov
@ 2023-03-31 15:12 ` Dmitry Baryshkov
  2023-03-31 19:42   ` Konrad Dybcio
  2023-04-10 15:18 ` [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Vinod Koul
  1 sibling, 1 reply; 4+ messages in thread
From: Dmitry Baryshkov @ 2023-03-31 15:12 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold

The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX
table is empty, so we can drop it completely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index f378c1ebefd7..df505279edfd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -725,9 +725,6 @@ static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 };
 
-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-};
-
 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
@@ -2212,8 +2209,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
 		.serdes_num	= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
 		.tx		= sdm845_qhp_pcie_tx_tbl,
 		.tx_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-		.rx		= sdm845_qhp_pcie_rx_tbl,
-		.rx_num		= ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
 		.pcs		= sdm845_qhp_pcie_pcs_tbl,
 		.pcs_num	= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
 	},
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl
  2023-03-31 15:12 ` [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl Dmitry Baryshkov
@ 2023-03-31 19:42   ` Konrad Dybcio
  0 siblings, 0 replies; 4+ messages in thread
From: Konrad Dybcio @ 2023-03-31 19:42 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
	Kishon Vijay Abraham I
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold



On 31.03.2023 17:12, Dmitry Baryshkov wrote:
> The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX
> table is empty, so we can drop it completely.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index f378c1ebefd7..df505279edfd 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -725,9 +725,6 @@ static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
>  	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
>  };
>  
> -static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
> -};
> -
>  static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
>  	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
>  	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
> @@ -2212,8 +2209,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
>  		.serdes_num	= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
>  		.tx		= sdm845_qhp_pcie_tx_tbl,
>  		.tx_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
> -		.rx		= sdm845_qhp_pcie_rx_tbl,
> -		.rx_num		= ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
>  		.pcs		= sdm845_qhp_pcie_pcs_tbl,
>  		.pcs_num	= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
>  	},

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes
  2023-03-31 15:12 [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Dmitry Baryshkov
  2023-03-31 15:12 ` [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl Dmitry Baryshkov
@ 2023-04-10 15:18 ` Vinod Koul
  1 sibling, 0 replies; 4+ messages in thread
From: Vinod Koul @ 2023-04-10 15:18 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm, linux-phy,
	Johan Hovold, stable

On 31-03-23, 18:12, Dmitry Baryshkov wrote:
> All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of
> lanes to 2.

Applied both, thanks

-- 
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^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-04-10 15:18 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-31 15:12 [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Dmitry Baryshkov
2023-03-31 15:12 ` [PATCH RESEND v2 2/2] phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl Dmitry Baryshkov
2023-03-31 19:42   ` Konrad Dybcio
2023-04-10 15:18 ` [PATCH RESEND v2 1/2] phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes Vinod Koul

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