[PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC

[PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC

[Siddharth Vadapalli]

Hello,

This series TI's J784S4 SoC. A new compatible is added for the J784S4 SoC,
with QSGMII mode enabled. Also, the CPSW9G instance of J784S4 SoC supports
USXGMII mode. Thus, add support to configure USXGMII mode.

Note:
This series is based on top of the following series:
https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/

The patch corresponding to the device-tree bindings for the compatible
"ti,j784s4-cpsw9g-phy-gmii-sel" is posted at:
https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com
Since the above patch has received an Acked-by from Krzysztof Kozlowski,
I am posting this series using the compatible.

Regards,
Siddharth.

Siddharth Vadapalli (2):
  phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4
  phy: ti: gmii-sel: Enable USXGMII mode for J784S4

 drivers/phy/ti/phy-gmii-sel.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

-- 
2.25.1


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[PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

[Siddharth Vadapalli]

Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.

Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
property for J784S4.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index c87118cb2af9..fba5c0c0771c 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
 	.num_qsgmii_main_ports = 2,
 };
 
+static const
+struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
+	.use_of_data = true,
+	.regfields = phy_gmii_sel_fields_am654,
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+	.num_ports = 8,
+	.num_qsgmii_main_ports = 2,
+};
+
 static const struct of_device_id phy_gmii_sel_id_table[] = {
 	{
 		.compatible	= "ti,am3352-phy-gmii-sel",
@@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = {
 		.compatible	= "ti,j721e-cpsw9g-phy-gmii-sel",
 		.data		= &phy_gmii_sel_cpsw9g_soc_j721e,
 	},
+	{
+		.compatible	= "ti,j784s4-cpsw9g-phy-gmii-sel",
+		.data		= &phy_gmii_sel_cpsw9g_soc_j784s4,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
-- 
2.25.1


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[PATCH 2/2] phy: ti: gmii-sel: Enable USXGMII mode for J784S4

[Siddharth Vadapalli]

TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC
ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's
SoC data.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/phy/ti/phy-gmii-sel.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index fba5c0c0771c..6286cf25a426 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -25,6 +25,7 @@
 /* J72xx SoC specific definitions for the CONTROL port */
 #define J72XX_GMII_SEL_MODE_SGMII	3
 #define J72XX_GMII_SEL_MODE_QSGMII	4
+#define J72XX_GMII_SEL_MODE_USXGMII	5
 #define J72XX_GMII_SEL_MODE_QSGMII_SUB	6
 
 #define PHY_GMII_PORT(n)	BIT((n) - 1)
@@ -114,6 +115,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
 			gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
 		break;
 
+	case PHY_INTERFACE_MODE_USXGMII:
+		if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII)))
+			goto unsupported;
+		else
+			gmii_sel_mode = J72XX_GMII_SEL_MODE_USXGMII;
+		break;
+
 	default:
 		goto unsupported;
 	}
@@ -239,7 +247,8 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
-	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
+		       BIT(PHY_INTERFACE_MODE_USXGMII),
 	.num_ports = 8,
 	.num_qsgmii_main_ports = 2,
 };
-- 
2.25.1


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Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

[Roger Quadros]

On 31/03/2023 09:25, Siddharth Vadapalli wrote:
> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.
> 
> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
> property for J784S4.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
> index c87118cb2af9..fba5c0c0771c 100644
> --- a/drivers/phy/ti/phy-gmii-sel.c
> +++ b/drivers/phy/ti/phy-gmii-sel.c
> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
>  	.num_qsgmii_main_ports = 2,
>  };
>  
> +static const
> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {

Please make it into one line

> +	.use_of_data = true,
> +	.regfields = phy_gmii_sel_fields_am654,
> +	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
> +	.num_ports = 8,
> +	.num_qsgmii_main_ports = 2,
> +};
> +
>  static const struct of_device_id phy_gmii_sel_id_table[] = {
>  	{
>  		.compatible	= "ti,am3352-phy-gmii-sel",
> @@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = {
>  		.compatible	= "ti,j721e-cpsw9g-phy-gmii-sel",
>  		.data		= &phy_gmii_sel_cpsw9g_soc_j721e,
>  	},
> +	{
> +		.compatible	= "ti,j784s4-cpsw9g-phy-gmii-sel",
> +		.data		= &phy_gmii_sel_cpsw9g_soc_j784s4,
> +	},
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
--
cheers,
-roger

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Re: [PATCH 2/2] phy: ti: gmii-sel: Enable USXGMII mode for J784S4

[Roger Quadros]

On 31/03/2023 09:25, Siddharth Vadapalli wrote:
> TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC
> ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's
> SoC data.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Reviewed-by: Roger Quadros <rogerq@kernel.org>

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Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

[Siddharth Vadapalli]

Hello Roger,

On 31/03/23 13:15, Roger Quadros wrote:
> 
> 
> On 31/03/2023 09:25, Siddharth Vadapalli wrote:
>> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.
>>
>> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
>> property for J784S4.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>  drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
>> index c87118cb2af9..fba5c0c0771c 100644
>> --- a/drivers/phy/ti/phy-gmii-sel.c
>> +++ b/drivers/phy/ti/phy-gmii-sel.c
>> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
>>  	.num_qsgmii_main_ports = 2,
>>  };
>>  
>> +static const
>> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
> 
> Please make it into one line

I was simply following the convention used for other SoC data structs in the
same file. Please let me know why this has to be an exception and I will post
the v2 series with the change accordingly.

Regards,
Siddharth.

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Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

[Roger Quadros]

On 31/03/2023 10:49, Siddharth Vadapalli wrote:
> Hello Roger,
> 
> On 31/03/23 13:15, Roger Quadros wrote:
>>
>>
>> On 31/03/2023 09:25, Siddharth Vadapalli wrote:
>>> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.
>>>
>>> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
>>> property for J784S4.
>>>
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>> ---
>>>  drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++
>>>  1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
>>> index c87118cb2af9..fba5c0c0771c 100644
>>> --- a/drivers/phy/ti/phy-gmii-sel.c
>>> +++ b/drivers/phy/ti/phy-gmii-sel.c
>>> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
>>>  	.num_qsgmii_main_ports = 2,
>>>  };
>>>  
>>> +static const
>>> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
>>
>> Please make it into one line
> 
> I was simply following the convention used for other SoC data structs in the
> same file. Please let me know why this has to be an exception and I will post
> the v2 series with the change accordingly.

Not that much of a deal. ;)

Reviewed-by: Roger Quadros <rogerq@kernel.org>

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Re: [PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC

[Vinod Koul]

On 31-03-23, 11:55, Siddharth Vadapalli wrote:
> Hello,
> 
> This series TI's J784S4 SoC. A new compatible is added for the J784S4 SoC,
> with QSGMII mode enabled. Also, the CPSW9G instance of J784S4 SoC supports
> USXGMII mode. Thus, add support to configure USXGMII mode.

Sorry this fails to apply for me, pls rebase and send

> 
> Note:
> This series is based on top of the following series:
> https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/
> 
> The patch corresponding to the device-tree bindings for the compatible
> "ti,j784s4-cpsw9g-phy-gmii-sel" is posted at:
> https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com
> Since the above patch has received an Acked-by from Krzysztof Kozlowski,
> I am posting this series using the compatible.
> 
> Regards,
> Siddharth.
> 
> Siddharth Vadapalli (2):
>   phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4
>   phy: ti: gmii-sel: Enable USXGMII mode for J784S4
> 
>  drivers/phy/ti/phy-gmii-sel.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> -- 
> 2.25.1

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Re: [PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC

[Siddharth Vadapalli]

Hello Vinod,

On 31-03-2023 19:03, Vinod Koul wrote:
> On 31-03-23, 11:55, Siddharth Vadapalli wrote:
>> Hello,
>>
>> This series TI's J784S4 SoC. A new compatible is added for the J784S4 SoC,
>> with QSGMII mode enabled. Also, the CPSW9G instance of J784S4 SoC supports
>> USXGMII mode. Thus, add support to configure USXGMII mode.
> 
> Sorry this fails to apply for me, pls rebase and send

This series has to be applied after the following series:
https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/
as mentioned below.

Regards,
Siddharth.
> 
>>
>> Note:
>> This series is based on top of the following series:
>> https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/
>>
>> The patch corresponding to the device-tree bindings for the compatible
>> "ti,j784s4-cpsw9g-phy-gmii-sel" is posted at:
>> https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com
>> Since the above patch has received an Acked-by from Krzysztof Kozlowski,
>> I am posting this series using the compatible.
>>
>> Regards,
>> Siddharth.
>>
>> Siddharth Vadapalli (2):
>>   phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4
>>   phy: ti: gmii-sel: Enable USXGMII mode for J784S4
>>
>>  drivers/phy/ti/phy-gmii-sel.c | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> -- 
>> 2.25.1
> 

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Re: [PATCH 0/2] PHY-GMII-SEL: Add support for J784S4 SoC

[Vinod Koul]

On 31-03-23, 19:19, Siddharth Vadapalli wrote:
> Hello Vinod,
> 
> On 31-03-2023 19:03, Vinod Koul wrote:
> > On 31-03-23, 11:55, Siddharth Vadapalli wrote:
> >> Hello,
> >>
> >> This series TI's J784S4 SoC. A new compatible is added for the J784S4 SoC,
> >> with QSGMII mode enabled. Also, the CPSW9G instance of J784S4 SoC supports
> >> USXGMII mode. Thus, add support to configure USXGMII mode.
> > 
> > Sorry this fails to apply for me, pls rebase and send
> 
> This series has to be applied after the following series:
> https://lore.kernel.org/r/20230309063514.398705-1-s-vadapalli@ti.com/
> as mentioned below.

Okay applied now

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