From: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
To: Roger Quadros <rogerq@kernel.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"kishon@kernel.org" <kishon@kernel.org>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: Milind Parab <mparab@cadence.com>
Subject: RE: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
Date: Mon, 27 Mar 2023 05:34:08 +0000 [thread overview]
Message-ID: <DM6PR07MB615438BAA6DA35E5FFE4737FC58B9@DM6PR07MB6154.namprd07.prod.outlook.com> (raw)
In-Reply-To: <c7bdaf8f-d377-9fdc-c11a-747c65775b3c@kernel.org>
Hi Vinod,
> -----Original Message-----
> From: Roger Quadros <rogerq@kernel.org>
> Sent: Monday, February 20, 2023 9:50 PM
> To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>;
> vkoul@kernel.org; kishon@kernel.org; linux-phy@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Cc: Milind Parab <mparab@cadence.com>
> Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
> configuration
>
> EXTERNAL MAIL
>
>
>
>
> On 20/02/2023 16:12, Swapnil Jakhade wrote:
> > Add register sequences for PCIe + SGMII PHY multilink configuration.
> > This has been validated on TI J7 platforms.
> >
> > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
>
> Reviewed-by: Roger Quadros <rogerq@kernel.org>
Could you please consider reviewing and merging this patch.
Thanks & regards,
Swapnil
--
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next prev parent reply other threads:[~2023-03-27 5:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-20 14:12 [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration Swapnil Jakhade
2023-02-20 16:20 ` Roger Quadros
2023-03-27 5:34 ` Swapnil Kashinath Jakhade [this message]
2023-03-31 13:44 ` Vinod Koul
2023-03-09 10:03 Siddharth Vadapalli
2023-03-09 10:12 ` Swapnil Kashinath Jakhade
2023-03-09 10:28 ` Siddharth Vadapalli
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