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From: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: "kishon@ti.com" <kishon@ti.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Milind Parab <mparab@cadence.com>,
	"a-govindraju@ti.com" <a-govindraju@ti.com>
Subject: RE: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
Date: Thu, 2 Dec 2021 14:12:51 +0000	[thread overview]
Message-ID: <DM6PR07MB61549C25EBF70ED2639FBCF6C5699@DM6PR07MB6154.namprd07.prod.outlook.com> (raw)
In-Reply-To: <YZ8aygJQoxie+Ddn@matsya>

Hi Vinod,

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Thursday, November 25, 2021 10:41 AM
> To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de; linux-
> phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> govindraju@ti.com
> Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
> multilink configuration
> 
> EXTERNAL MAIL
> 
> 
> On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:
> 
> > > so this is pcie->qsgmii ->ssc/external/internal ... ok
> > >
> > > > +				[NO_SSC] =
> > > &pcie_100_no_ssc_plllc_cmn_vals,
> > > > +				[EXTERNAL_SSC] =
> > > &pcie_100_ext_ssc_plllc_cmn_vals,
> > > > +				[INTERNAL_SSC] =
> > > &pcie_100_int_ssc_plllc_cmn_vals,
> > > > +			},
> > > >  		},
> > > >  		[TYPE_USB] = {
> > > >  			[TYPE_NONE] = {
> > > >  				[EXTERNAL_SSC] =
> > > &usb_100_ext_ssc_cmn_vals,
> > > >  			},
> > > >  		},
> > > > +		[TYPE_QSGMII] = {
> > > > +			[TYPE_PCIE] = {
> > >
> > > now it is reverse! qsgmii -> pcie -> ... why?
> > >
> > > what is meant by pcie->qsgmii and qsgmii-> pcie?
> > >
> >
> > Multi-protocol configuration is done in 2 phases, each for one protocol.
> > e.g. for PCIe + QSGMII case,
> > [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers for
> > PCIe and [TYPE_QSGMII][TYPE_PCIE] will configure common and lane
> registers for QSGMII.
> 
> Then it should be always common + protocol or protocol + common, not
> both please! Pls make an order and stick to it everywhere... If that is not
> possible, I would like to understand why
> 

Could you please elaborate what do you mean by
" common + protocol or protocol + common, not both please!"?
The order is same everywhere which is common + lane configuration for protocol 1
and then for protocol 2. For multiprotocol case, PHY configuration is based on which
protocols are operating simultaneously. So e.g.
[TYPE_QSGMII][TYPE_PCIE] -> QSGMII configuration when other protocol is PCIe
Which might be different than
[TYPE_QSGMII][TYPE_*] -> QSGMII configuration with other protocol.

Thanks & regards,
Swapnil

> --
> ~Vinod

-- 
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  reply	other threads:[~2021-12-02 14:13 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 17:02 [PATCH v3 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-11-23  4:33   ` Vinod Koul
2021-11-24  7:32     ` Swapnil Kashinath Jakhade
2021-10-22 17:02 ` [PATCH v3 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-11-23  4:48   ` Vinod Koul
2021-11-24  7:33     ` Swapnil Kashinath Jakhade
2021-11-25  5:10       ` Vinod Koul
2021-12-02 14:12         ` Swapnil Kashinath Jakhade [this message]
2021-12-09  6:11           ` Milind Parab
2021-12-09 11:50             ` Vinod Koul
2021-12-09 11:53           ` Vinod Koul
2021-12-10  9:46             ` Swapnil Kashinath Jakhade
2021-12-14  9:22               ` Vinod Koul
2021-10-22 17:02 ` [PATCH v3 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
2021-12-09  7:55 ` [PATCH v3 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Kishon Vijay Abraham I

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