From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Philipp Zabel <p.zabel@pengutronix.de>,
Jack Zhu <jack.zhu@starfivetech.com>,
<linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v2 2/3] phy: starfive: Add mipi dphy rx support
Date: Mon, 3 Apr 2023 09:39:00 +0800 [thread overview]
Message-ID: <d48ab612-213a-8d20-4b36-3f64f3d24721@starfivetech.com> (raw)
In-Reply-To: <ZCbloBdeffocT3Os@matsya>
On 2023/3/31 21:52, Vinod Koul wrote:
> On 21-03-23, 14:08, Changhuang Liang wrote:
>>
>>
>> On 2023/3/20 20:37, Vinod Koul wrote:
>>> On 22-02-23, 17:59, Changhuang Liang wrote:
>>>> [...]
>>>> +static const struct regval_t stf_dphy_init_list[] = {
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(4), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(8), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(12), 0x0000fff0 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(16), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(20), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(24), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(28), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(32), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(36), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(48), 0x24000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(52), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(56), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(60), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(64), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(68), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(72), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(76), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(80), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(84), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(88), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(92), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(96), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(100), 0x02000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(104), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(108), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(112), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(116), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(120), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(124), 0x0000000c },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(128), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(132), 0xcc500000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(136), 0x000000cc },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(140), 0x00000000 },
>>>> + { STF_DPHY_APBCFGSAIF__SYSCFG(144), 0x00000000 },
>>>> +};
>>>> +
>>>> +static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
>>>> +{
>>>> + struct stf_dphy *dphy = phy_get_drvdata(phy);
>>>> + int map[6] = {4, 0, 1, 2, 3, 5};
>>>
>>> what does this mean?
>>
>> This is the physical lane and logical lane mapping table, should I add a note for it?
>
> Yes please. Also will the mapping be always static or ever change?
>
The mapping is always static on the visionfive2 single board computer.
Thanks for your comments.
>>
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(stf_dphy_init_list); i++)
>>>> + writel(stf_dphy_init_list[i].val,
>>>> + dphy->regs + stf_dphy_init_list[i].addr);
>>>> +
>>>> + writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) |
>>>> + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) |
>>>> + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) |
>>>> + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b),
>>>> + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(0));
>>>> +
>>>> + writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) |
>>>> + FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a),
>>>> + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(184));
>>>> [...]
>>>> +module_platform_driver(stf_dphy_driver);
>>>> +
>>>> +MODULE_AUTHOR("Jack Zhu <jack.zhu@starfivetech.com>");
>>>> +MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
>>>> +MODULE_DESCRIPTION("Starfive DPHY RX driver");
>>>> +MODULE_LICENSE("GPL");
>>>> --
>>>> 2.25.1
>>>
>
--
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linux-phy@lists.infradead.org
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next prev parent reply other threads:[~2023-04-03 1:39 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-23 1:59 [PATCH v2 0/3] Add JH7110 MIPI DPHY RX support Changhuang Liang
2023-02-23 1:59 ` [PATCH v2 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Changhuang Liang
2023-02-27 18:34 ` Rob Herring
2023-02-28 8:55 ` Changhuang Liang
2023-02-23 1:59 ` [PATCH v2 2/3] phy: starfive: Add mipi dphy rx support Changhuang Liang
2023-03-20 12:37 ` Vinod Koul
2023-03-21 6:08 ` Changhuang Liang
2023-03-31 13:52 ` Vinod Koul
2023-04-03 1:39 ` Changhuang Liang [this message]
2023-04-03 6:24 ` Conor Dooley
2023-04-03 6:31 ` Changhuang Liang
2023-04-03 6:34 ` Vinod Koul
2023-04-03 6:39 ` Changhuang Liang
2023-02-23 1:59 ` [PATCH v2 3/3] riscv: dts: starfive: Add dphy rx node Changhuang Liang
2023-03-03 6:05 ` [PATCH v2 0/3] Add JH7110 MIPI DPHY RX support Changhuang Liang
2023-03-20 12:39 ` Vinod Koul
2023-03-21 2:09 ` Changhuang Liang
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