From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
Georgi Djakov <georgi.djakov@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v1 12/29] interconnect: Add memory interconnection providers for NVIDIA Tegra SoCs
Date: Tue, 19 Nov 2019 19:59:58 +0300 [thread overview]
Message-ID: <044b17a8-7186-fec0-e786-5ec5a13e5873@gmail.com> (raw)
In-Reply-To: <20191119063139.GF2462695@ulmo>
19.11.2019 09:31, Thierry Reding пишет:
> On Mon, Nov 18, 2019 at 11:02:30PM +0300, Dmitry Osipenko wrote:
> [...]
>> diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
>> index 1238e35653d1..593954324259 100644
>> --- a/include/soc/tegra/mc.h
>> +++ b/include/soc/tegra/mc.h
>> @@ -141,6 +141,11 @@ struct tegra_mc_reset_ops {
>> const struct tegra_mc_reset *rst);
>> };
>>
>> +struct tegra_mc_icc_node {
>> + const char *name;
>> + unsigned int id;
>> +};
>> +
>> struct tegra_mc_soc {
>> const struct tegra_mc_client *clients;
>> unsigned int num_clients;
>> @@ -160,6 +165,9 @@ struct tegra_mc_soc {
>> const struct tegra_mc_reset_ops *reset_ops;
>> const struct tegra_mc_reset *resets;
>> unsigned int num_resets;
>> +
>> + const struct tegra_mc_icc_node *icc_nodes;
>> + unsigned int num_icc_nodes;
>> };
>>
>> struct tegra_mc {
>> @@ -184,4 +192,22 @@ struct tegra_mc {
>> int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
>> unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
>>
>> +#ifdef CONFIG_INTERCONNECT_TEGRA
>> +int tegra_icc_mc_setup_interconnect(struct tegra_mc *mc);
>> +int tegra_icc_emc_setup_interconnect(struct device *emc_dev,
>> + unsigned int dram_data_bus_width_bytes);
>> +#else
>> +static inline int tegra_icc_mc_setup_interconnect(struct tegra_mc *mc);
>> +{
>> + return 0;
>> +}
>> +
>> +static inline int
>> +tegra_icc_emc_setup_interconnect(struct device *emc_dev,
>> + unsigned int dram_data_bus_width_bytes)
>> +{
>> + return 0;
>> +}
>> +#endif
>
> Is there really any reason why we should make this support optional? It
> seems to me like we would always want this enabled once it's tested and
> known to work.
There is always some room for bugs, should be better to have an option
to disable ICC entirely (IMO).
next prev parent reply other threads:[~2019-11-19 17:00 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 20:02 [PATCH v1 00/29] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 01/29] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 02/29] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2019-11-19 6:21 ` Thierry Reding
2019-11-19 16:57 ` Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 03/29] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 04/29] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 05/29] dt-bindings: memory: tegra124: mc: " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 06/29] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 07/29] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 08/29] dt-bindings: interconnect: tegra: Add initial IDs Dmitry Osipenko
2019-11-19 6:25 ` Thierry Reding
2019-11-19 16:56 ` Dmitry Osipenko
2019-11-21 17:14 ` Dmitry Osipenko
2019-11-25 11:32 ` Thierry Reding
2019-11-28 20:06 ` Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 09/29] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 10/29] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 11/29] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko
2019-11-19 6:27 ` Thierry Reding
2019-11-18 20:02 ` [PATCH v1 12/29] interconnect: Add memory interconnection providers for NVIDIA Tegra SoCs Dmitry Osipenko
2019-11-19 6:30 ` Thierry Reding
2019-11-19 16:58 ` Dmitry Osipenko
2019-11-21 17:33 ` Dmitry Osipenko
2019-11-19 6:31 ` Thierry Reding
2019-11-19 16:59 ` Dmitry Osipenko [this message]
2019-11-18 20:02 ` [PATCH v1 13/29] memory: tegra: Register as interconnect provider Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 14/29] memory: tegra: Add interconnect nodes for Terga20 display controllers Dmitry Osipenko
2019-11-19 6:34 ` Thierry Reding
2019-11-18 20:02 ` [PATCH v1 15/29] memory: tegra: Add interconnect nodes for Terga30 " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 16/29] memory: tegra: Add interconnect nodes for Terga124 " Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 17/29] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 18/29] memory: tegra20-emc: Continue probing if timings/IRQ are missing in device-tree Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 19/29] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 20/29] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 21/29] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 22/29] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 23/29] memory: tegra124-emc: Register as interconnect provider Dmitry Osipenko
2019-11-19 16:57 ` Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 24/29] drm/tegra: dc: Use devm_platform_ioremap_resource Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 25/29] drm/tegra: dc: Release PM and RGB output when client's registration fails Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 26/29] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 27/29] ARM: tegra: Enable interconnect API in tegra_defconfig Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 28/29] ARM: multi_v7_defconfig: Enable NVIDIA Tegra interconnect providers Dmitry Osipenko
2019-11-18 20:02 ` [PATCH v1 29/29] MAINTAINERS: Add maintainers for NVIDIA Tegra interconnect drivers Dmitry Osipenko
2019-11-19 6:19 ` [PATCH v1 00/29] Introduce memory interconnect for NVIDIA Tegra SoCs Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=044b17a8-7186-fec0-e786-5ec5a13e5873@gmail.com \
--to=digetx@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=georgi.djakov@linaro.org \
--cc=jonathanh@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mperttunen@nvidia.com \
--cc=pdeschrijver@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).