From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <tglx@linutronix.de>,
<jason@lakedaemon.net>, <marc.zyngier@arm.com>,
<linus.walleij@linaro.org>, <stefan@agner.ch>,
<mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
<rjw@rjwysocki.net>, <viresh.kumar@linaro.org>,
<linux-pm@vger.kernel.org>
Subject: Re: [PATCH v8 10/21] clk: tegra: clk-super: Add restore-context support
Date: Fri, 9 Aug 2019 10:08:50 -0700 [thread overview]
Message-ID: <12250cae-8850-ff1d-91b1-0a50cdab6fa1@nvidia.com> (raw)
In-Reply-To: <4e33bad9-8d5a-dcd7-c75e-db5843c9be4a@gmail.com>
On 8/9/19 5:17 AM, Dmitry Osipenko wrote:
> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>> This patch implements restore_context for clk_super_mux and clk_super.
>>
>> During system supend, core power goes off the and context of Tegra
>> CAR registers is lost.
>>
>> So on system resume, context of super clock registers are restored
>> to have them in same state as before suspend.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-super.c | 21 +++++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
>> index e2a1e95a8db7..74c9e913e41c 100644
>> --- a/drivers/clk/tegra/clk-super.c
>> +++ b/drivers/clk/tegra/clk-super.c
>> @@ -124,9 +124,18 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
>> return err;
>> }
>>
>> +static void clk_super_mux_restore_context(struct clk_hw *hw)
>> +{
>> + struct clk_hw *parent = clk_hw_get_parent(hw);
>> + int parent_id = clk_hw_get_parent_index(hw, parent);
>> +
>> + clk_super_set_parent(hw, parent_id);
> All Super clocks have a divider, including the "MUX". Thus I'm wondering
> if there is a chance that divider's configuration may differ on resume
> from what it was on suspend.
tegra_clk_register_super_mux which uses tegra_clk_super_mux_ops doesn't
do divider rate programming.
I believe you are referring to sclk_divider, cclklp_divider,
cclkg_divider...
these are registered as clk_divider and are restored during clk_divider
resume.
>> +}
>> +
>> static const struct clk_ops tegra_clk_super_mux_ops = {
>> .get_parent = clk_super_get_parent,
>> .set_parent = clk_super_set_parent,
>> + .restore_context = clk_super_mux_restore_context,
>> };
>>
>> static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
>> @@ -162,12 +171,24 @@ static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
>> return super->div_ops->set_rate(div_hw, rate, parent_rate);
>> }
>>
>> +static void clk_super_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
>> + struct clk_hw *div_hw = &super->frac_div.hw;
>> + struct clk_hw *parent = clk_hw_get_parent(hw);
>> + int parent_id = clk_hw_get_parent_index(hw, parent);
>> +
>> + super->div_ops->restore_context(div_hw);
>> + clk_super_set_parent(hw, parent_id);
>> +}
>> +
>> const struct clk_ops tegra_clk_super_ops = {
>> .get_parent = clk_super_get_parent,
>> .set_parent = clk_super_set_parent,
>> .set_rate = clk_super_set_rate,
>> .round_rate = clk_super_round_rate,
>> .recalc_rate = clk_super_recalc_rate,
>> + .restore_context = clk_super_restore_context,
>> };
>>
>> struct clk *tegra_clk_register_super_mux(const char *name,
>>
next prev parent reply other threads:[~2019-08-09 17:08 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-08 23:46 [PATCH v8 00/21] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 01/21] pinctrl: tegra: Fix write barrier placement in pmx_writel Sowjanya Komatineni
2019-08-09 11:38 ` Dmitry Osipenko
2019-08-12 9:20 ` Thierry Reding
2019-08-14 8:32 ` Linus Walleij
2019-08-08 23:46 ` [PATCH v8 02/21] pinctrl: tegra: Add write barrier after all pinctrl register writes Sowjanya Komatineni
2019-08-09 11:39 ` Dmitry Osipenko
2019-08-12 9:20 ` Thierry Reding
2019-08-14 8:33 ` Linus Walleij
2019-08-08 23:46 ` [PATCH v8 03/21] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-08-12 9:21 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 04/21] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-08-11 18:04 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-08-09 11:33 ` Dmitry Osipenko
2019-08-09 17:39 ` Sowjanya Komatineni
2019-08-09 17:50 ` Dmitry Osipenko
2019-08-09 18:50 ` Sowjanya Komatineni
2019-08-11 17:24 ` Dmitry Osipenko
2019-08-09 12:46 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 06/21] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 07/21] clk: Add API to get index of the clock parent Sowjanya Komatineni
2019-08-09 11:49 ` Dmitry Osipenko
2019-08-12 9:47 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 08/21] clk: tegra: periph: Add restore_context support Sowjanya Komatineni
2019-08-09 11:55 ` Dmitry Osipenko
2019-08-09 12:20 ` Dmitry Osipenko
2019-08-09 16:55 ` Sowjanya Komatineni
2019-08-12 9:50 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-08-09 12:11 ` Dmitry Osipenko
2019-08-12 9:53 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 10/21] clk: tegra: clk-super: Add restore-context support Sowjanya Komatineni
2019-08-09 12:17 ` Dmitry Osipenko
2019-08-09 17:08 ` Sowjanya Komatineni [this message]
2019-08-11 17:29 ` Dmitry Osipenko
2019-08-12 9:55 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 11/21] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-08-09 12:23 ` Dmitry Osipenko
2019-08-09 16:39 ` Sowjanya Komatineni
2019-08-09 18:00 ` Dmitry Osipenko
2019-08-09 18:33 ` Sowjanya Komatineni
2019-08-09 18:52 ` Dmitry Osipenko
2019-08-12 10:01 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 12/21] cpufreq: tegra124: " Sowjanya Komatineni
2019-08-12 10:07 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 13/21] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-08-11 18:02 ` Dmitry Osipenko
2019-08-11 19:16 ` Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 14/21] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-08-09 13:56 ` Dmitry Osipenko
2019-08-09 16:19 ` Sowjanya Komatineni
2019-08-09 18:18 ` Dmitry Osipenko
[not found] ` <cbe94f84-a17b-7e1a-811d-89db571784e1@nvidia.com>
2019-08-11 17:39 ` Dmitry Osipenko
2019-08-11 19:15 ` Sowjanya Komatineni
2019-08-12 16:25 ` Dmitry Osipenko
2019-08-12 17:28 ` Sowjanya Komatineni
2019-08-12 18:19 ` Dmitry Osipenko
2019-08-12 19:03 ` Sowjanya Komatineni
2019-08-12 20:28 ` Dmitry Osipenko
2019-08-12 10:17 ` Thierry Reding
2019-08-08 23:46 ` [PATCH v8 15/21] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-08-11 17:52 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 16/21] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-08-09 13:28 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 17/21] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-08-08 23:46 ` [PATCH v8 18/21] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-08-09 13:13 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 19/21] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-08-09 13:23 ` Dmitry Osipenko
2019-08-09 16:23 ` Sowjanya Komatineni
2019-08-09 17:24 ` Sowjanya Komatineni
2019-08-09 18:22 ` Dmitry Osipenko
2019-08-08 23:46 ` [PATCH v8 20/21] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-08-08 23:47 ` [PATCH v8 21/21] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
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