From: Catalin Marinas <catalin.marinas@arm.com>
To: Lina Iyer <lina.iyer@linaro.org>
Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"khilman@linaro.org" <khilman@linaro.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"daniel.lezcano@linaro.org" <daniel.lezcano@linaro.org>,
"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"msivasub@codeaurora.org" <msivasub@codeaurora.org>,
"galak@codeaurora.org" <galak@codeaurora.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v13 03/10] qcom: spm: Add Subsystem Power Manager driver
Date: Tue, 2 Dec 2014 11:10:17 +0000 [thread overview]
Message-ID: <20141202111017.GC26306@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <20141201185705.GC499@linaro.org>
On Mon, Dec 01, 2014 at 06:57:05PM +0000, Lina Iyer wrote:
> On Thu, Nov 27 2014 at 08:01 -0700, Lorenzo Pieralisi wrote:
> >On Thu, Nov 27, 2014 at 05:24:07AM +0000, Lina Iyer wrote:
> >
> >[...]
> >
> >> +static int spm_set_low_power_mode(enum pm_sleep_mode mode)
> >> +{
> >> + struct spm_driver_data *drv = per_cpu(cpu_spm_drv,
> >> + smp_processor_id());
> >> + u32 start_index;
> >> + u32 ctl_val;
> >> +
> >> + if (!drv)
> >> + return -ENXIO;
> >> +
> >> + start_index = drv->reg_data->start_index[mode];
> >> +
> >> + ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
> >> + ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
> >> + ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
> >> + ctl_val |= SPM_CTL_EN;
> >> + spm_register_write(drv, SPM_REG_SPM_CTL, ctl_val);
> >> +
> >> + /* Ensure we have written the start address */
> >> + wmb();
> >
> >Can you explain please what this wmb is meant to achieve ? If it is there
> >to make sure the write made it to the SPM that's not a proper way
> >to achieve it, the barrier ensures ordering, not write completion.
>
> A write completion would be great, but assuming that the context switch
> using SCM or WFI could ensure the flush, then ordering is probably good
> enough for this.
I assume you want the write to the device to complete (side-effects are
observed) before the WFI (which would raise a StandbyWFI signal). The
safer way is to read back from the device (or check/poll for the device
state change) rather than a barrier.
--
Catalin
next prev parent reply other threads:[~2014-12-02 11:10 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-27 5:24 [PATCH v13 00/10] cpuidle driver for QCOM SoCs: 8064, 8074, 8084 Lina Iyer
2014-11-27 5:24 ` [PATCH v13 01/10] qcom: scm: Move scm-boot files to drivers/soc/qcom/ and include/soc/qcom Lina Iyer
2014-11-27 5:24 ` [PATCH v13 02/10] qcom: scm: Add SCM warmboot support for quad core SoCs Lina Iyer
2014-11-27 5:24 ` [PATCH v13 03/10] qcom: spm: Add Subsystem Power Manager driver Lina Iyer
2014-11-27 8:44 ` Ivan T. Ivanov
2014-12-01 17:57 ` Lina Iyer
2014-11-27 8:52 ` Daniel Lezcano
2014-12-01 18:50 ` Lina Iyer
2014-12-02 9:53 ` Daniel Lezcano
2014-12-02 15:35 ` Lina Iyer
2014-12-02 15:47 ` Daniel Lezcano
2014-11-27 15:01 ` Lorenzo Pieralisi
2014-12-01 18:57 ` Lina Iyer
2014-12-02 11:10 ` Catalin Marinas [this message]
2014-12-02 15:52 ` Lina Iyer
2014-11-27 5:24 ` [PATCH v13 04/10] arm: dts: qcom: Add power-controller device node for 8074 Krait CPUs Lina Iyer
2014-11-27 5:24 ` [PATCH v13 05/10] arm: dts: qcom: Add power-controller device node for 8084 " Lina Iyer
2014-11-27 5:24 ` [PATCH v13 06/10] arm: dts: qcom: Update power-controller device node for 8064 " Lina Iyer
2014-11-27 5:24 ` [PATCH v13 07/10] qcom: cpuidle: Add cpuidle driver for QCOM cpus Lina Iyer
2014-11-27 5:24 ` [PATCH v13 08/10] arm: dts: qcom: Add idle states device nodes for 8074 Lina Iyer
2014-11-27 5:24 ` [PATCH v13 09/10] arm: dts: qcom: Add idle states device nodes for 8084 Lina Iyer
2014-11-27 5:24 ` [PATCH v13 10/10] arm: dts: qcom: Add idle state device nodes for 8064 Lina Iyer
2014-11-27 8:53 ` [PATCH v13 00/10] cpuidle driver for QCOM SoCs: 8064, 8074, 8084 Daniel Lezcano
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