From mboxrd@z Thu Jan 1 00:00:00 1970 From: Viresh Kumar Subject: Re: [RFC v2 09/11] drm/msm/dpu: Use OPP API to set clk/perf state Date: Wed, 10 Apr 2019 09:19:28 +0530 Message-ID: <20190410034928.wkfnebwmcdonhto6@vireshk-i7> References: <20190320094918.20234-1-rnayak@codeaurora.org> <20190320094918.20234-10-rnayak@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190320094918.20234-10-rnayak@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Rajendra Nayak Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, dianders@chromium.org, rafael@kernel.org List-Id: linux-pm@vger.kernel.org On 20-03-19, 15:19, Rajendra Nayak wrote: > On some qualcomm platforms DPU needs to express a perforamnce state > requirement on a power domain depennding on the clock rates. > Use OPP table from DT to register with OPP framework and use > dev_pm_opp_set_rate() to set the clk/perf state. > > Signed-off-by: Rajendra Nayak > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ++++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 +++++++++ > 2 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > index 9f20f397f77d..db21a86b242b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -298,7 +299,11 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate) > rate = core_clk->max_rate; > > core_clk->rate = rate; > - return msm_dss_clk_set_rate(core_clk, 1); > + > + if (dev_pm_opp_get_opp_table(&kms->pdev->dev)) This takes a reference of the OPP table, you need to call put thing as well to balance it off. > + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate); > + else > + return msm_dss_clk_set_rate(core_clk, 1); > } -- viresh From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_NEOMUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7468C10F14 for ; Wed, 10 Apr 2019 03:49:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 913A92075B for ; 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Tue, 09 Apr 2019 20:49:30 -0700 (PDT) Date: Wed, 10 Apr 2019 09:19:28 +0530 From: Viresh Kumar To: Rajendra Nayak Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-scsi@vger.kernel.org, swboyd@chromium.org, ulf.hansson@linaro.org, dianders@chromium.org, rafael@kernel.org Subject: Re: [RFC v2 09/11] drm/msm/dpu: Use OPP API to set clk/perf state Message-ID: <20190410034928.wkfnebwmcdonhto6@vireshk-i7> References: <20190320094918.20234-1-rnayak@codeaurora.org> <20190320094918.20234-10-rnayak@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline In-Reply-To: <20190320094918.20234-10-rnayak@codeaurora.org> User-Agent: NeoMutt/20180323-120-3dd1ac Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Message-ID: <20190410034928.fcuyyfSIbqZF_vZOfafb4bUmrwRGVg7bi1sb78EWvv0@z> On 20-03-19, 15:19, Rajendra Nayak wrote: > On some qualcomm platforms DPU needs to express a perforamnce state > requirement on a power domain depennding on the clock rates. > Use OPP table from DT to register with OPP framework and use > dev_pm_opp_set_rate() to set the clk/perf state. > > Signed-off-by: Rajendra Nayak > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ++++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 +++++++++ > 2 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > index 9f20f397f77d..db21a86b242b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -298,7 +299,11 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate) > rate = core_clk->max_rate; > > core_clk->rate = rate; > - return msm_dss_clk_set_rate(core_clk, 1); > + > + if (dev_pm_opp_get_opp_table(&kms->pdev->dev)) This takes a reference of the OPP table, you need to call put thing as well to balance it off. > + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate); > + else > + return msm_dss_clk_set_rate(core_clk, 1); > } -- viresh