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From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, sboyd@kernel.org,
	b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
	cw00.choi@samsung.com, kyungmin.park@samsung.com,
	m.szyprowski@samsung.com, s.nawrocki@samsung.com,
	myungjoo.ham@samsung.com, keescook@chromium.org,
	tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
	digetx@gmail.com, gregkh@linuxfoundation.org,
	willy.mh.wolff.ml@gmail.com,
	Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v10 12/13] ARM: dts: exynos: add DMC device for exynos5422
Date: Fri, 14 Jun 2019 11:53:08 +0200
Message-ID: <20190614095309.24100-13-l.luba@partner.samsung.com> (raw)
In-Reply-To: <CGME20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4@eucas1p1.samsung.com>

Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
There is a definition of the memory chip, which is then used during
calculation of timings for each OPP.
The algorithm in the driver needs these two sets to bound the timings.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi             |  73 +++++++++++
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 116 ++++++++++++++++++
 2 files changed, 189 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index d153617ff1a3..79e74ae80938 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -235,6 +235,31 @@
 			status = "disabled";
 		};
 
+		dmc: memory-controller@10c20000 {
+			compatible = "samsung,exynos5422-dmc";
+			reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
+			clocks = <&clock CLK_FOUT_SPLL>,
+				 <&clock CLK_MOUT_SCLK_SPLL>,
+				 <&clock CLK_FF_DOUT_SPLL2>,
+				 <&clock CLK_FOUT_BPLL>,
+				 <&clock CLK_MOUT_BPLL>,
+				 <&clock CLK_SCLK_BPLL>,
+				 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+				 <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+				 <&clock CLK_MOUT_MCLK_CDREX>;
+			clock-names = "fout_spll",
+				      "mout_sclk_spll",
+				      "ff_dout_spll2",
+				      "fout_bpll",
+				      "mout_bpll",
+				      "sclk_bpll",
+				      "mout_mx_mspll_ccore",
+				      "mout_mx_mspll_ccore_phy",
+				      "mout_mclk_cdrex";
+			samsung,syscon-clk = <&clock>;
+			status = "disabled";
+		};
+
 		nocp_mem0_0: nocp@10ca1000 {
 			compatible = "samsung,exynos5420-nocp";
 			reg = <0x10CA1000 0x200>;
@@ -271,6 +296,54 @@
 			status = "disabled";
 		};
 
+		ppmu_dmc0_0: ppmu@10d00000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d00000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+					event-name = "ppmu-event3-dmc0_0";
+				};
+			};
+		};
+
+		ppmu_dmc0_1: ppmu@10d10000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d10000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+					event-name = "ppmu-event3-dmc0_1";
+				};
+			};
+		};
+
+		ppmu_dmc1_0: ppmu@10d60000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d60000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+					event-name = "ppmu-event3-dmc1_0";
+				};
+			};
+		};
+
+		ppmu_dmc1_1: ppmu@10d70000 {
+			compatible = "samsung,exynos-ppmu";
+			reg = <0x10d70000 0x2000>;
+			clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+			clock-names = "ppmu";
+			events {
+				ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+					event-name = "ppmu-event3-dmc1_1";
+				};
+			};
+		};
+
 		gsc_pd: power-domain@10044000 {
 			compatible = "samsung,exynos4210-pd";
 			reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..30e569c13ee7 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -34,6 +34,97 @@
 			clock-frequency = <24000000>;
 		};
 	};
+
+	dmc_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <165000000>;
+			opp-microvolt = <875000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <206000000>;
+			opp-microvolt = <875000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <275000000>;
+			opp-microvolt = <875000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <413000000>;
+			opp-microvolt = <887500>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <543000000>;
+			opp-microvolt = <937500>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <633000000>;
+			opp-microvolt = <1012500>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <728000000>;
+			opp-microvolt = <1037500>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <825000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	samsung_K3QF2F20DB: lpddr3 {
+		compatible	= "samsung,K3QF2F20DB", "jedec,lpddr3";
+		density		= <16384>;
+		io-width	= <32>;
+		#address-cells  = <1>;
+		#size-cells     = <0>;
+
+		tRFC-min-tck		= <17>;
+		tRRD-min-tck		= <2>;
+		tRPab-min-tck		= <2>;
+		tRPpb-min-tck		= <2>;
+		tRCD-min-tck		= <3>;
+		tRC-min-tck		= <6>;
+		tRAS-min-tck		= <5>;
+		tWTR-min-tck		= <2>;
+		tWR-min-tck		= <7>;
+		tRTP-min-tck		= <2>;
+		tW2W-C2C-min-tck	= <0>;
+		tR2R-C2C-min-tck	= <0>;
+		tWL-min-tck		= <8>;
+		tDQSCK-min-tck		= <5>;
+		tRL-min-tck		= <14>;
+		tFAW-min-tck		= <5>;
+		tXSR-min-tck		= <12>;
+		tXP-min-tck		= <2>;
+		tCKE-min-tck		= <2>;
+		tCKESR-min-tck		= <2>;
+		tMRD-min-tck		= <5>;
+
+		timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+			compatible	= "jedec,lpddr3-timings";
+			reg		= <800000000>; /* workaround: it shows max-freq */
+			min-freq	= <100000000>;
+			tRFC		= <65000>;
+			tRRD		= <6000>;
+			tRPab		= <12000>;
+			tRPpb		= <12000>;
+			tRCD		= <10000>;
+			tRC		= <33750>;
+			tRAS		= <23000>;
+			tWTR		= <3750>;
+			tWR		= <7500>;
+			tRTP		= <3750>;
+			tW2W-C2C	= <0>;
+			tR2R-C2C	= <0>;
+			tFAW		= <25000>;
+			tXSR		= <70000>;
+			tXP		= <3750>;
+			tCKE		= <3750>;
+			tCKESR		= <3750>;
+			tMRD		= <7000>;
+		};
+	};
 };
 
 &adc {
@@ -132,6 +223,15 @@
 	cpu-supply = <&buck2_reg>;
 };
 
+&dmc {
+	devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,
+			<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+	device-handle = <&samsung_K3QF2F20DB>;
+	operating-points-v2 = <&dmc_opp_table>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
 &hsi2c_4 {
 	status = "okay";
 
@@ -540,6 +640,22 @@
 	};
 };
 
+&ppmu_dmc0_0 {
+	status = "okay";
+};
+
+&ppmu_dmc0_1 {
+	status = "okay";
+};
+
+&ppmu_dmc1_0 {
+	status = "okay";
+};
+
+&ppmu_dmc1_1 {
+	status = "okay";
+};
+
 &tmu_cpu0 {
 	vtmu-supply = <&ldo7_reg>;
 };
-- 
2.17.1


  parent reply index

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20190614095319eucas1p2d47b6bd9179c7e4190972d6b22092ad7@eucas1p2.samsung.com>
2019-06-14  9:52 ` [PATCH v10 00/13] Exynos5 Dynamic Memory Controller driver Lukasz Luba
     [not found]   ` <CGME20190614095320eucas1p2919a6169c997bb81c80416e8a0ede538@eucas1p2.samsung.com>
2019-06-14  9:52     ` [PATCH v10 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-06-14 12:04       ` Krzysztof Kozlowski
2019-06-14 12:38         ` Sylwester Nawrocki
2019-06-14 12:39           ` Krzysztof Kozlowski
     [not found]   ` <CGME20190614095321eucas1p2af62f3cdf78ba3c5a8013159da4f7502@eucas1p2.samsung.com>
2019-06-14  9:52     ` [PATCH v10 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
     [not found]   ` <CGME20190614095323eucas1p1312dd7bcc5a25cbb3af28ed0f52dc7a6@eucas1p1.samsung.com>
2019-06-14  9:52     ` [PATCH v10 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
     [not found]   ` <CGME20190614095324eucas1p2eab4def0ed8c912303e4bb3e422bb255@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 04/13] dt-bindings: ddr: rename lpddr2 directory Lukasz Luba
     [not found]   ` <CGME20190614095324eucas1p247ee87a9ca69733e7aebd601f5d96a94@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 05/13] dt-bindings: ddr: add LPDDR3 memories Lukasz Luba
     [not found]   ` <CGME20190614095325eucas1p20083d9290b36eca945ec3f1428bdbd4f@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 06/13] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
2019-06-14 12:43       ` Krzysztof Kozlowski
2019-08-22 13:34         ` Lukasz Luba
     [not found]   ` <CGME20190614095326eucas1p22e27d86d886d7a33acdd59c7f0f6d7d8@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
     [not found]   ` <CGME20190614095327eucas1p19b6e522efa15c8fd21c51f3900e376e9@eucas1p1.samsung.com>
2019-06-14  9:53     ` [PATCH v10 08/13] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-06-14 12:09       ` Krzysztof Kozlowski
2019-06-14 12:58       ` Krzysztof Kozlowski
2019-06-14 13:40         ` Lukasz Luba
2019-06-14 13:46           ` Krzysztof Kozlowski
2019-06-14 13:47       ` Krzysztof Kozlowski
2019-06-25 11:26         ` Lukasz Luba
     [not found]   ` <CGME20190614095328eucas1p24009b3a07322fd12e49eabb7a08baf50@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 09/13] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
2019-06-22 13:10       ` Chanwoo Choi
2019-06-25  7:31         ` Lukasz Luba
2019-06-25  7:38           ` Chanwoo Choi
     [not found]   ` <CGME20190614095329eucas1p267244e53d4f5612c46d6cc2c6bc0ed75@eucas1p2.samsung.com>
2019-06-14  9:53     ` [PATCH v10 10/13] ARM: dts: exynos: add chipid label and syscon compatible Lukasz Luba
     [not found]   ` <CGME20190614095330eucas1p1e5a73f31251af7d16caf951054ec9def@eucas1p1.samsung.com>
2019-06-14  9:53     ` [PATCH v10 11/13] ARM: dts: exynos: add syscon to clock compatible Lukasz Luba
     [not found]   ` <CGME20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4@eucas1p1.samsung.com>
2019-06-14  9:53     ` Lukasz Luba [this message]
     [not found]   ` <CGME20190614095332eucas1p10e0a690604c6210d5f61c55175532785@eucas1p1.samsung.com>
2019-06-14  9:53     ` [PATCH v10 13/13] ARM: exynos_defconfig: enable DMC driver Lukasz Luba

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