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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id 68sm5857904otw.56.2019.11.04.14.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 14:01:45 -0800 (PST) Date: Mon, 4 Nov 2019 16:01:44 -0600 From: Rob Herring To: Leonard Crestez Cc: Stephen Boyd , MyungJoo Ham , Kyungmin Park , "Rafael J. Wysocki" , Shawn Guo , Chanwoo Choi , Mark Rutland , Michael Turquette , Artur =?utf-8?B?xZp3aWdvxYQ=?= , Saravana Kannan , Angus Ainslie , Martin Kepplinger , Matthias Kaehlcke , Krzysztof Kozlowski , Alexandre Bailon , Georgi Djakov , Dong Aisheng , Abel Vesa , Jacky Bai , Anson Huang , Fabio Estevam , Viresh Kumar , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 6/6] arm64: dts: imx8m: Add ddr controller nodes Message-ID: <20191104220144.GA5218@bogus> References: <44dcab5a136f5b046092e6ed456d8e206413059f.1572558427.git.leonard.crestez@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44dcab5a136f5b046092e6ed456d8e206413059f.1572558427.git.leonard.crestez@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Thu, Oct 31, 2019 at 11:50:27PM +0200, Leonard Crestez wrote: > This is used by the imx-ddrc devfreq driver to implement dynamic > frequency scaling of DRAM. > > Add a devfreq-event link to the dram PMU in order to support on-demand > scaling of ddrc based on measured dram bandwidth usage. > > Support for proactive scaling via interconnect will come later. The > high-performance bus masters which need that (display, vpu, gpu) are not > yet enabled in upstream anyway. > > Signed-off-by: Leonard Crestez > --- > arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 17 ++++++++++++- > .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 16 ++++++++++++- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 16 ++++++++++++- > 6 files changed, 106 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > index 4f5e408d6e6a..be9abd8e4478 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > @@ -69,16 +69,34 @@ > simple-audio-card,codec { > sound-dai = <&wm8524>; > clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; > }; > }; > + > + ddrc_opp_table: ddrc-opp-table { > + compatible = "operating-points-v2"; > + > + opp-25M { > + opp-hz = /bits/ 64 <25000000>; > + }; > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + opp-750M { > + opp-hz = /bits/ 64 <750000000>; > + }; > + }; > }; > > &A53_0 { > cpu-supply = <&buck2_reg>; > }; > > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > +}; > + > &fec1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_fec1>; > phy-mode = "rgmii-id"; > phy-handle = <ðphy0>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 6edbdfe2d0d7..5404870d80d5 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -856,11 +856,26 @@ > #interrupt-cells = <3>; > interrupt-controller; > interrupts = ; > }; > > - ddr-pmu@3d800000 { > + ddrc: dram-controller@3d400000 { > + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; > + reg = <0x3d400000 0x400000>; Do you really need the OS to map 4MB of register space? Virtual space on 64-bit doesn't matter, but it's still wasting 2KB of memory just to map all that if only a few pages are needed. Adds up if the whole DT is done this way. > + clock-names = "dram_core", > + "dram_pll", > + "dram_alt", > + "dram_apb"; > + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, > + <&clk IMX8MM_DRAM_PLL>, > + <&clk IMX8MM_CLK_DRAM_ALT>, > + <&clk IMX8MM_CLK_DRAM_APB>; > + devfreq-events = <&ddr_pmu>; > + operating-points-v2 = <&ddrc_opp_table>; > + }; > + > + ddr_pmu: ddr-pmu@3d800000 { > compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; > reg = <0x3d800000 0x400000>; > interrupt-parent = <&gic>; > interrupts = ; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts > index 071949412caf..ab2060667671 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts > @@ -9,16 +9,34 @@ > #include "imx8mn-evk.dtsi" > > / { > model = "NXP i.MX8MNano DDR4 EVK board"; > compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; > + > + ddrc_opp_table: ddrc-opp-table { I think it would be better to put this under the ddrc node (and named 'opp-table'). Yes, it's kind of silly to have a phandle to a child node, but that still works. > + compatible = "operating-points-v2"; > + > + opp-25M { > + opp-hz = /bits/ 64 <25000000>; > + }; > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + opp-600M { > + opp-hz = /bits/ 64 <600000000>; > + }; > + }; > }; > > &A53_0 { > cpu-supply = <&buck2_reg>; > }; > > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > +}; > + > &i2c1 { > pmic@4b { > compatible = "rohm,bd71847"; > reg = <0x4b>; > pinctrl-0 = <&pinctrl_pmic>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index e91625063f8e..344dd777635f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -757,11 +757,25 @@ > #interrupt-cells = <3>; > interrupt-controller; > interrupts = ; > }; > > - ddr-pmu@3d800000 { > + ddrc: dram-controller@3d400000 { > + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; > + reg = <0x3d400000 0x400000>; > + clock-names = "dram_core", > + "dram_pll", > + "dram_alt", > + "dram_apb"; > + clocks = <&clk IMX8MN_CLK_DRAM_CORE>, > + <&clk IMX8MN_DRAM_PLL>, > + <&clk IMX8MN_CLK_DRAM_ALT>, > + <&clk IMX8MN_CLK_DRAM_APB>; > + devfreq-events = <&ddr_pmu>; > + }; > + > + ddr_pmu: ddr-pmu@3d800000 { > compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; > reg = <0x3d800000 0x400000>; > interrupts = ; > }; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index c36685916683..fc4c12ab8991 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -85,10 +85,30 @@ > link_codec: simple-audio-card,codec { > sound-dai = <&wm8524>; > clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; > }; > }; > + > + ddrc_opp_table: ddrc-opp-table { > + compatible = "operating-points-v2"; > + > + opp-25M { > + opp-hz = /bits/ 64 <25000000>; > + }; > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + /* > + * On imx8mq B0 PLL can't be bypassed so low bus is 166M > + */ > + opp-166M { > + opp-hz = /bits/ 64 <166935483>; > + }; > + opp-800M { > + opp-hz = /bits/ 64 <800000000>; > + }; > + }; > }; > > &A53_0 { > cpu-supply = <&buck2_reg>; > }; > @@ -103,10 +123,14 @@ > > &A53_3 { > cpu-supply = <&buck2_reg>; > }; > > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > +}; > + > &fec1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_fec1>; > phy-mode = "rgmii-id"; > phy-handle = <ðphy0>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 7f9319452b58..6ef1af41ef68 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1111,11 +1111,25 @@ > interrupt-controller; > interrupts = ; > interrupt-parent = <&gic>; > }; > > - ddr-pmu@3d800000 { > + ddrc: dram-controller@3d400000 { > + compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; > + reg = <0x3d400000 0x400000>; > + clock-names = "dram_core", > + "dram_pll", > + "dram_alt", > + "dram_apb"; > + clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, > + <&clk IMX8MQ_DRAM_PLL_OUT>, > + <&clk IMX8MQ_CLK_DRAM_ALT>, > + <&clk IMX8MQ_CLK_DRAM_APB>; > + devfreq-events = <&ddr_pmu>; > + }; > + > + ddr_pmu: ddr-pmu@3d800000 { > compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; > reg = <0x3d800000 0x400000>; > interrupt-parent = <&gic>; > interrupts = ; > }; > -- > 2.17.1 >