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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id d6sm3494169oth.45.2019.11.04.14.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 14:21:27 -0800 (PST) Date: Mon, 4 Nov 2019 16:21:26 -0600 From: Rob Herring To: Leonard Crestez Cc: Stephen Boyd , MyungJoo Ham , Kyungmin Park , "Rafael J. Wysocki" , Shawn Guo , Chanwoo Choi , Mark Rutland , Michael Turquette , Artur =?utf-8?B?xZp3aWdvxYQ=?= , Saravana Kannan , Angus Ainslie , Martin Kepplinger , Matthias Kaehlcke , Krzysztof Kozlowski , Alexandre Bailon , Georgi Djakov , Dong Aisheng , Abel Vesa , Jacky Bai , Anson Huang , Fabio Estevam , Viresh Kumar , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 3/6] dt-bindings: devfreq: Add bindings for imx ddr controller Message-ID: <20191104222126.GB5218@bogus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Thu, Oct 31, 2019 at 11:50:24PM +0200, Leonard Crestez wrote: > Add devicetree bindings for the i.MX DDR Controller on imx8m series > chips. It supports dynamic frequency switching between multiple data > rates and this is exposed to Linux via the devfreq subsystem. > > Signed-off-by: Leonard Crestez > --- > .../devicetree/bindings/devfreq/imx-ddrc.yaml | 60 +++++++++++++++++++ .../bindings/memory-controllers/ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml > > diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml > new file mode 100644 > index 000000000000..31db204e6845 > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: GPL-2.0 For new bindings: # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/devfreq/imx-devfreq.yaml# Run 'make dt_binding_check'. This will fail as the filename doesn't match. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX DDR Controller Perhaps i.MX8x as it's not all i.MX chips. And the filename too? > + > +maintainers: > + - Leonard Crestez > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,imx8mn-ddrc > + - fsl,imx8mm-ddrc > + - fsl,imx8mq-ddrc > + - const: fsl,imx8m-ddrc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: dram_core > + - const: dram_pll > + - const: dram_alt > + - const: dram_apb Drop 'dram_' > + > + operating-points-v2: true > + > + devfreq-events: > + description: Phandle of PMU node > + $ref: "/schemas/types.yaml#/definitions/phandle" > + > +required: > + - reg > + - compatible > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + ddrc: dram-controller@3d400000 { > + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; > + reg = <0x3d400000 0x400000>; > + clock-names = "dram_core", "dram_pll", "dram_alt", "dram_apb"; > + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, > + <&clk IMX8MM_DRAM_PLL>, > + <&clk IMX8MM_CLK_DRAM_ALT>, > + <&clk IMX8MM_CLK_DRAM_APB>; > + operating-points-v2 = <&ddrc_opp_table>; > + }; > -- > 2.17.1 >