From: Shawn Guo <shawnguo@kernel.org>
To: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "Stephen Boyd" <sboyd@kernel.org>,
"Chanwoo Choi" <cw00.choi@samsung.com>,
"Rob Herring" <robh+dt@kernel.org>,
"MyungJoo Ham" <myungjoo.ham@samsung.com>,
"Kyungmin Park" <kyungmin.park@samsung.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
"Mark Rutland" <mark.rutland@arm.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Artur Świgoń" <a.swigon@partner.samsung.com>,
"Saravana Kannan" <saravanak@google.com>,
"Angus Ainslie" <angus@akkea.ca>,
"Martin Kepplinger" <martink@posteo.de>,
"Matthias Kaehlcke" <mka@chromium.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Alexandre Bailon" <abailon@baylibre.com>,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>,
"Anson Huang" <Anson.Huang@nxp.com>,
"Fabio Estevam" <fabio.estevam@nxp.com>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Silvano di Ninno" <silvano.dininno@nxp.com>,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes
Date: Mon, 9 Dec 2019 09:34:15 +0800 [thread overview]
Message-ID: <20191209013414.GS3365@dragon> (raw)
In-Reply-To: <23e46c12c98947315229c20dea6784ad40d294c4.1574458460.git.leonard.crestez@nxp.com>
On Fri, Nov 22, 2019 at 11:45:04PM +0200, Leonard Crestez wrote:
> This is used by the imx-ddrc devfreq driver to implement dynamic
> frequency scaling of DRAM.
>
> Support for proactive scaling via interconnect will come later. The
> high-performance bus masters which need that (display, vpu, gpu) are
> mostly not yet enabled in upstream anyway.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 ++++++++
> .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 ++++++++
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++
> 6 files changed, 90 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index 28ab17a277bb..ecf0d385c164 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -75,10 +75,28 @@
>
> &A53_0 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
As an idiomatic practice, we have newline between nodes.
I fixed it up and applied the patch.
Shawn
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + opp-750M {
> + opp-hz = /bits/ 64 <750000000>;
> + };
> + };
> +};
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec1>;
> phy-mode = "rgmii-id";
> phy-handle = <ðphy0>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 6edbdfe2d0d7..3d4802375715 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -856,10 +856,20 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> index 071949412caf..b051c927c11e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> @@ -15,10 +15,28 @@
>
> &A53_0 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + opp-600M {
> + opp-hz = /bits/ 64 <600000000>;
> + };
> + };
> +};
> +
> &i2c1 {
> pmic@4b {
> compatible = "rohm,bd71847";
> reg = <0x4b>;
> pinctrl-0 = <&pinctrl_pmic>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index e91625063f8e..3a79fdddc72b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -757,10 +757,20 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
> + <&clk IMX8MN_DRAM_PLL>,
> + <&clk IMX8MN_CLK_DRAM_ALT>,
> + <&clk IMX8MN_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index c36685916683..ee6dc5f07622 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -103,10 +103,34 @@
>
> &A53_3 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + /*
> + * On imx8mq B0 PLL can't be bypassed so low bus is 166M
> + */
> + opp-166M {
> + opp-hz = /bits/ 64 <166935483>;
> + };
> + opp-800M {
> + opp-hz = /bits/ 64 <800000000>;
> + };
> + };
> +};
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec1>;
> phy-mode = "rgmii-id";
> phy-handle = <ðphy0>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 7f9319452b58..d1fcf9887f8b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1111,10 +1111,20 @@
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
> + <&clk IMX8MQ_DRAM_PLL_OUT>,
> + <&clk IMX8MQ_CLK_DRAM_ALT>,
> + <&clk IMX8MQ_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-12-09 1:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-22 21:44 [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez
2019-11-22 21:45 ` [PATCH v7 1/5] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez
2019-12-09 1:15 ` Shawn Guo
2019-11-22 21:45 ` [PATCH v7 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez
2019-12-09 1:16 ` Shawn Guo
2019-11-22 21:45 ` [PATCH v7 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez
2019-11-22 21:45 ` [PATCH v7 4/5] PM / devfreq: Add dynamic scaling " Leonard Crestez
2019-11-24 23:59 ` Chanwoo Choi
2019-11-26 19:44 ` Rob Herring
2019-11-26 23:25 ` Chanwoo Choi
[not found] ` <CGME20191219230258epcas1p16ec64c3a06eafd9f0a3784d18541ce5c@epcas1p1.samsung.com>
2019-12-19 23:09 ` [v8 PATCH] " Chanwoo Choi
2019-12-19 23:10 ` Chanwoo Choi
2019-11-22 21:45 ` [PATCH v7 5/5] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez
2019-11-28 14:43 ` Adam Ford
2019-11-29 5:33 ` Leonard Crestez
2019-12-09 1:34 ` Shawn Guo [this message]
2019-12-18 13:35 ` [PATCH v7 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Adam Ford
2019-12-18 14:44 ` Leonard Crestez
2019-12-18 15:05 ` Adam Ford
2019-12-18 15:16 ` Leonard Crestez
2019-12-18 15:37 ` Adam Ford
2019-12-18 16:22 ` Leonard Crestez
2019-12-18 16:42 ` Adam Ford
[not found] ` <CAHCN7xKjpN_XEGLj-1jMG5mBbF=su67k+10frheLt+L1XaR0-g@mail.gmail.com>
2020-01-13 23:36 ` Leonard Crestez
2020-01-15 20:09 ` Adam Ford
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