From: Shawn Guo <shawnguo@kernel.org>
To: peng.fan@nxp.com
Cc: viresh.kumar@linaro.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
Anson.Huang@nxp.com, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/3] ARM: dts: imx: add nvmem property for cpu0
Date: Wed, 11 Mar 2020 16:30:52 +0800 [thread overview]
Message-ID: <20200311083052.GD29269@dragon> (raw)
In-Reply-To: <1583201690-16068-2-git-send-email-peng.fan@nxp.com>
On Tue, Mar 03, 2020 at 10:14:48AM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add nvmem related property for cpu0, then nvmem API could be used
> to read cpu speed grading to avoid directly read OCOTP registers
> mapped which could not handle defer probe.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/boot/dts/imx6dl.dtsi | 2 ++
> arch/arm/boot/dts/imx6q.dtsi | 2 ++
> arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
> arch/arm/boot/dts/imx6sl.dtsi | 9 +++++++++
> arch/arm/boot/dts/imx6sll.dtsi | 6 ++++++
> arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++
> 6 files changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 4b3a128d9260..055f1d875bac 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -44,6 +44,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
>
> cpu@1 {
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 0fad13f9d336..d3ba9d4a1290 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -49,6 +49,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
>
> cpu1: cpu@1 {
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 70fb8b56b1d7..982f546b0b89 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1165,6 +1165,13 @@
> compatible = "fsl,imx6q-ocotp", "syscon";
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6QDL_CLK_IIM>;
> +
Please drop such newline. Do not really think they are necessary.
Shawn
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> };
>
> tzasc@21d0000 { /* TZASC1 */
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index c8ec46fe8302..de943341e4f2 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -74,6 +74,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -953,6 +955,13 @@
> compatible = "fsl,imx6sl-ocotp", "syscon";
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SL_CLK_OCOTP>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> };
>
> audmux: audmux@21d8000 {
> diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
> index 797f850492fe..6b7fb3cec9f6 100644
> --- a/arch/arm/boot/dts/imx6sll.dtsi
> +++ b/arch/arm/boot/dts/imx6sll.dtsi
> @@ -72,6 +72,8 @@
> <&clks IMX6SLL_CLK_PLL1_SYS>;
> clock-names = "arm", "pll2_pfd2_396m", "step",
> "pll1_sw", "pll1_sys";
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -791,6 +793,10 @@
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SLL_CLK_OCOTP>;
>
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> +
> tempmon_calib: calib@38 {
> reg = <0x38 4>;
> };
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index e47d346a3543..63aa19d81b42 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -87,6 +87,8 @@
> "pll1_sw", "pll1_sys";
> arm-supply = <®_arm>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -1058,6 +1060,10 @@
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SX_CLK_OCOTP>;
>
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> +
> tempmon_calib: calib@38 {
> reg = <0x38 4>;
> };
> --
> 2.16.4
>
next prev parent reply other threads:[~2020-03-11 8:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 2:14 [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API peng.fan
2020-03-03 2:14 ` [PATCH 1/3] ARM: dts: imx: add nvmem property for cpu0 peng.fan
2020-03-11 8:30 ` Shawn Guo [this message]
2020-03-03 2:14 ` [PATCH 2/3] cpufreq: imx6q: fix error handling peng.fan
2020-03-03 2:14 ` [PATCH 3/3] cpufreq: imx6q: read OCOTP through nvmem for imx6q peng.fan
2020-03-03 5:45 ` [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API Viresh Kumar
2020-03-03 6:16 ` Peng Fan
2020-03-03 11:17 ` Viresh Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200311083052.GD29269@dragon \
--to=shawnguo@kernel.org \
--cc=Anson.Huang@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=peng.fan@nxp.com \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).