From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: "Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Paul Burton" <paulburton@kernel.org>,
"Ralf Baechle" <ralf@linux-mips.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Rob Herring" <robh+dt@kernel.org>,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Alexander Lobakin" <alobakin@dlink.ru>,
"Huacai Chen" <chenhc@lemote.com>,
"Cedric Hombourger" <Cedric_Hombourger@mentor.com>,
"René van Dorst" <opensource@vdorst.com>,
"Ard Biesheuvel" <ardb@kernel.org>,
"Jessica Yu" <jeyu@kernel.org>,
"Masahiro Yamada" <masahiroy@kernel.org>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support
Date: Fri, 8 May 2020 14:21:37 +0200 [thread overview]
Message-ID: <20200508122137.GA13177@alpha.franken.de> (raw)
In-Reply-To: <20200508093259.GB9085@alpha.franken.de>
On Fri, May 08, 2020 at 11:32:59AM +0200, Thomas Bogendoerfer wrote:
> On Fri, May 08, 2020 at 12:19:23AM +0300, Serge Semin wrote:
> > On Thu, May 07, 2020 at 01:17:35PM +0200, Thomas Bogendoerfer wrote:
> > > P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
> > > above/below ?
> >
> > Alas, We can't do this so easy. CONFIG_CPU_MIPS32_{R2,R5,R6} and any other
> > CONFIG_CPU_* configs is something that kernel config-file is supposed to select.
> > Their availability is enabled by the CONFIG_SYS_HAS_CPU_* configs. CONFIG_CPU_*
> > is supposed to activate CPU-specific features and there is only one
> > CONFIG_CPU_x can be enabled at a time seeing it's a part of the "CPU type"
> > choice kconfig menu. In addition the CPU config also tunes a compiler to activate
> > the arch-specific ISA and optimizations in the arch/mips/Makefile by setting
> > -march=cpu-name (where cpu-name can be p5600, mips32r5, etc).
> >
> > Yes, P5600 is based on the MIPS32r5, but it also has got some specific features
> > (see config CPU_P5600 and config MIPS32_R5), which makes it to be different from
> > the ancestor. So In addition to the difficulties described above IMHO converting
> > CPU_P5600 to a set of features activated on top of the CPU_MIPS32_R5 config
> > would contradict the design of the CPU-support configs implemented in the MIPS
> > arch subsystem.
>
> maybe I wasn't clear enough, my suggestion is
>
> use
>
> config CPU_P5600
> bool "MIPS Warrior P5600"
> depends on SYS_HAS_CPU_P5600
> select CPU_MIPS32_R5
> select CPU_SUPPORTS_UNCACHED_ACCELERATED
> select CPU_SUPPORTS_CPUFREQ
> select CPU_MIPSR2_IRQ_VI
> select CPU_MIPSR2_IRQ_EI
>
> That way you don't need to any "|| CPU_P5600" where CPU_MIPS32_R5 is
> already there. Or are there cases, where this would be wrong ?
nevermind, this would also need a select SYS_HAS_CPU_MIPS32_R5, which
isn't wanted here. So patch is fine as is.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2020-05-08 12:30 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 12:46 [PATCH 00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 00/20] " Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:04 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC Sergey.Semin
2020-05-06 17:55 ` Sam Ravnborg
2020-05-06 19:20 ` Serge Semin
2020-05-06 19:26 ` Sam Ravnborg
2020-05-06 20:18 ` Serge Semin
2020-05-14 18:13 ` Serge Semin
2020-05-14 18:31 ` Rob Herring
2020-05-06 17:42 ` [PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR Sergey.Semin
2020-05-07 11:10 ` Thomas Bogendoerfer
2020-05-07 21:32 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:38 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 06/20] mips: Add MIPS32 Release 5 support Sergey.Semin
2020-05-08 13:30 ` Thomas Bogendoerfer
2020-05-10 22:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:19 ` Serge Semin
2020-05-08 9:32 ` Thomas Bogendoerfer
2020-05-08 12:21 ` Thomas Bogendoerfer [this message]
2020-05-10 22:09 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Sergey.Semin
2020-05-08 13:28 ` Thomas Bogendoerfer
2020-05-10 23:59 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 09/20] mips: Add CP0 Write Merge config support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 11/20] mips: MAAR: Use more precise address mask Sergey.Semin
2020-05-07 11:09 ` Thomas Bogendoerfer
2020-05-07 19:13 ` Serge Semin
2020-05-08 9:22 ` Thomas Bogendoerfer
2020-05-10 22:13 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 12/20] mips: MAAR: Add XPA mode support Sergey.Semin
2020-05-19 15:42 ` Thomas Bogendoerfer
2020-05-20 11:30 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Sergey.Semin
2020-05-06 18:16 ` Sergei Shtylyov
2020-05-06 19:52 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment Sergey.Semin
2020-05-08 12:15 ` Jiaxun Yang
2020-05-06 17:42 ` [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled Sergey.Semin
2020-05-08 15:41 ` Thomas Bogendoerfer
2020-05-11 13:31 ` Serge Semin
2020-05-15 7:48 ` Serge Semin
2020-05-15 21:06 ` Thomas Bogendoerfer
2020-05-16 11:55 ` Serge Semin
2020-05-18 13:48 ` Serge Semin
2020-05-18 16:32 ` Thomas Bogendoerfer
2020-05-18 20:57 ` Serge Semin
2020-05-19 15:50 ` Thomas Bogendoerfer
2020-05-20 11:59 ` Serge Semin
2020-05-20 14:03 ` Serge Semin
2020-05-20 18:40 ` Thomas Bogendoerfer
2020-05-20 21:13 ` Serge Semin
2020-05-20 12:12 ` Serge Semin
2020-05-20 12:21 ` Serge Semin
2020-05-20 13:38 ` Thomas Bogendoerfer
2020-05-20 13:48 ` Serge Semin
2020-05-20 18:30 ` Thomas Bogendoerfer
2020-05-20 21:12 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Sergey.Semin
2020-05-08 15:40 ` Thomas Bogendoerfer
2020-05-11 0:34 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting Sergey.Semin
2020-05-15 15:58 ` Rafael J. Wysocki
2020-05-16 12:52 ` Serge Semin
2020-05-18 7:41 ` Viresh Kumar
2020-05-18 9:53 ` Rafael J. Wysocki
2020-05-18 10:11 ` Viresh Kumar
2020-05-18 10:22 ` Rafael J. Wysocki
2020-05-18 10:24 ` Viresh Kumar
2020-05-18 10:31 ` Serge Semin
2020-05-18 10:41 ` Rafael J. Wysocki
2020-05-18 10:46 ` Serge Semin
2020-05-18 10:51 ` Rafael J. Wysocki
2020-05-18 10:56 ` Serge Semin
2020-05-18 11:05 ` Rafael J. Wysocki
2020-05-19 1:50 ` Xiongfeng Wang
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