From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
Pavel Machek <pavel@ucw.cz>, Rob Herring <robh+dt@kernel.org>
Cc: Sandeep Tripathy <milun.tripathy@gmail.com>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Liush <liush@allwinnertech.com>, Anup Patel <anup@brainfault.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v5 4/8] RISC-V: Add SBI HSM suspend related defines
Date: Wed, 2 Jun 2021 16:53:17 +0530 [thread overview]
Message-ID: <20210602112321.2241566-5-anup.patel@wdc.com> (raw)
In-Reply-To: <20210602112321.2241566-1-anup.patel@wdc.com>
We add defines related to SBI HSM suspend call and also
update HSM states naming as-per latest SBI specification.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/sbi.h | 27 ++++++++++++++++++++++-----
arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 289621da4a2a..ab9782f8da52 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -62,15 +62,32 @@ enum sbi_ext_hsm_fid {
SBI_EXT_HSM_HART_START = 0,
SBI_EXT_HSM_HART_STOP,
SBI_EXT_HSM_HART_STATUS,
+ SBI_EXT_HSM_HART_SUSPEND,
};
-enum sbi_hsm_hart_status {
- SBI_HSM_HART_STATUS_STARTED = 0,
- SBI_HSM_HART_STATUS_STOPPED,
- SBI_HSM_HART_STATUS_START_PENDING,
- SBI_HSM_HART_STATUS_STOP_PENDING,
+enum sbi_hsm_hart_state {
+ SBI_HSM_STATE_STARTED = 0,
+ SBI_HSM_STATE_STOPPED,
+ SBI_HSM_STATE_START_PENDING,
+ SBI_HSM_STATE_STOP_PENDING,
+ SBI_HSM_STATE_SUSPENDED,
+ SBI_HSM_STATE_SUSPEND_PENDING,
+ SBI_HSM_STATE_RESUME_PENDING,
};
+#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
+#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
+#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
+
+#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
+#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
+#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
+#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
+#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
+ SBI_HSM_SUSP_PLAT_BASE)
+#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
+ SBI_HSM_SUSP_BASE_MASK)
+
enum sbi_ext_srst_fid {
SBI_EXT_SRST_RESET = 0,
};
diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c
index 685fae72b7f5..5fd90f03a3e9 100644
--- a/arch/riscv/kernel/cpu_ops_sbi.c
+++ b/arch/riscv/kernel/cpu_ops_sbi.c
@@ -97,7 +97,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid)
rc = sbi_hsm_hart_get_status(hartid);
- if (rc == SBI_HSM_HART_STATUS_STOPPED)
+ if (rc == SBI_HSM_STATE_STOPPED)
return 0;
return rc;
}
--
2.25.1
next prev parent reply other threads:[~2021-06-02 11:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 11:23 [PATCH v5 0/8] RISC-V CPU Idle Support Anup Patel
2021-06-02 11:23 ` [PATCH v5 1/8] RISC-V: Enable CPU_IDLE drivers Anup Patel
2021-06-02 11:23 ` [PATCH v5 2/8] RISC-V: Rename relocate() and make it global Anup Patel
2021-06-02 11:23 ` [PATCH v5 3/8] RISC-V: Add arch functions for non-retentive suspend entry/exit Anup Patel
2021-06-02 11:23 ` Anup Patel [this message]
2021-06-02 11:23 ` [PATCH v5 5/8] cpuidle: Factor-out power domain related code from PSCI domain driver Anup Patel
2021-06-02 13:17 ` Ulf Hansson
2021-06-02 15:06 ` Anup Patel
2021-06-06 18:34 ` Samuel Holland
2021-06-09 8:01 ` Anup Patel
2021-06-02 11:23 ` [PATCH v5 6/8] cpuidle: Add RISC-V SBI CPU idle driver Anup Patel
2021-06-06 18:39 ` Samuel Holland
2021-06-09 10:36 ` Anup Patel
2021-06-02 11:23 ` [PATCH v5 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states Anup Patel
2021-06-02 11:23 ` [PATCH v5 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Anup Patel
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