From: Doug Smythies <dsmythies@telus.net>
To: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Giovanni Gherdovich <ggherdovich@suse.cz>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Len Brown <lenb@kernel.org>,
Linux PM list <linux-pm@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
dsmythies <dsmythies@telus.net>
Subject: Re: [PATCH v2] cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode
Date: Tue, 7 Sep 2021 20:43:19 -0700 [thread overview]
Message-ID: <CAAYoRsVd4uU7sofcvYWd__evKJTf7HE5mi2ZVDjAYNYWXS3mzQ@mail.gmail.com> (raw)
In-Reply-To: <7abae13c235d74f4789cd93c6c6b0cbf69df243d.camel@linux.intel.com>
On Tue, Sep 7, 2021 at 7:04 PM Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
>
> On Tue, 2021-09-07 at 13:16 -0700, Doug Smythies wrote:
> > Hi Srinivas, Thank you for your reply.
> >
> > On Tue, Sep 7, 2021 at 9:01 AM Srinivas Pandruvada
> > <srinivas.pandruvada@linux.intel.com> wrote:
> > > On Tue, 2021-09-07 at 08:45 -0700, Doug Smythies wrote:
> > > >
> > > > Recent ASUS BIOS updates have changed the default system
> > > > response for this old thread, rendering "intel_pstate=no_hwp"
> > > > useless.
> > > >
> > > > It also raises a question: If BIOS has forced HWP, then how do we
> > > > prevent the acpi-cpufreq driver from being used? Read on.
> > >
> > > Does BIOS has option to enable Intel speed shift with no legacy
> > > support?
> > > Then this option will not populate ACPI _PSS table.
> >
> > The option is there no matter what.
> > I have tried every variation of legacy or no legacy that
> > I can find. Currently:
> > Current boot mode: UEFI Firmware mode
> > SecureBoot: disabled
> >
> > >
> > > >
> > > > On Fri, May 14, 2021 at 3:12 PM Doug Smythies <
> > > > dsmythies@telus.net>
> > > > wrote:
> > > > >
> > > > > On Fri, May 14, 2021 at 1:33 PM Giovanni Gherdovich <
> > > > > ggherdovich@suse.cz> wrote:
> > > > > > On Fri, 2021-05-14 at 08:31 -0700, Doug Smythies wrote:
> > > > ...
> > > > > >
> > ...
> > > > Previous correspondence was with BIOS version 1003. There have
> > > > been 3
> > > > BIOS
> > > > releases since then (at least that I know of), 2103, 2201, 2301,
> > > > and
> > > > all of them
> > > > have changed the behaviour of the "Auto" setting for Intel Speed
> > > > Shift
> > > > Technology BIOS setting, forcing it on upon transfer of control
> > > > to
> > > > the OS.
> > > >
> > > > Where with "intel_pstate=no_hwp" one used to get 0 for
> > > > MSR_PM_ENABLE
> > > > (0x770) they now get 1.
> > >
> > > So they are forcing Out of band OOB mode.
> > > Does bit 8 or 18 in MSR 0x1aa is set?
> >
> > No.
>
> So there is no legacy path. I think you are working with their support.
Yes, for almost a month now, with very little to show for it.
We'll see what happens. I did get a message this afternoon:
"Our GTSD is debugging the issue,.
When they have the result, they will directly update you."
> In HWP mode does setting scaling min/max frequency has any impact?
No. I wouldn't have expected it to, as the system is confused as to who
is in charge. The acpi-cpufreq driver thinks it is in charge, but HWP
thinks it is.
The intel_pstate driver works fine.
... Doug
>
> Thanks,
> Srinivas
>
> >
> > Here is the output from my msr reader/decoder program.
> > Kernel 5.14 (unpatched).
> > intel_pstate=disable
> > BIOS setting "Auto" for Intel Speed Shift,
> > Driver: acpi-cpufreq
> >
> > doug@s19:~$ sudo c/msr-decoder
> > How many CPUs?: 12
> > 8.) 0x198: IA32_PERF_STATUS : CPU 0-11 : 45 : 45 : 45 : 45 :
> > 45 : 45 : 45 : 45 : 45 : 45 : 45 : 45 :
> > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable
> > 1.) 0x19C: IA32_THERM_STATUS: 88450000
> > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination
> > enabled
> > OOB Bit 8 reset OOB Bit 18 reset
> > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88410000
> > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0
> > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO
> > disable
> > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 10B2930 : high 48 :
> > guaranteed 41 : efficient 11 : lowest 1
> > 6.) 0x774: IA32_HWP_REQUEST: CPU 0-11 :
> > raw: 80003001 : 80003001 : 80003001 : 80003001 : 80003001 :
> > 80003001 : 80003001 : 80003001 : 80003001 : 80003001 : 80003001 :
> > 80003001 :
> > min: 1 : 1 : 1 : 1 : 1 :
> > 1 : 1 : 1 : 1 : 1 : 1 : 1 :
> > max: 48 : 48 : 48 : 48 : 48 :
> > 48 : 48 : 48 : 48 : 48 : 48 : 48
> > :
> > des: 0 : 0 : 0 : 0 : 0 :
> > 0 : 0 : 0 : 0 : 0 : 0 : 0 :
> > epp: 128 : 128 : 128 : 128 : 128 :
> > 128 : 128 : 128 : 128 : 128 : 128 : 128
> > :
> > act: 0 : 0 : 0 : 0 : 0 :
> > 0 : 0 : 0 : 0 : 0 : 0 : 0 :
> > 7.) 0x777: IA32_HWP_STATUS: 0 : high 0 : guaranteed 0 : efficient 0 :
> > lowest 0
> >
> > ...
> >
> > ... Doug
>
>
next prev parent reply other threads:[~2021-09-08 3:43 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-13 7:59 [PATCH] cpufreq: intel_pstate: Force intel_pstate to load when HWP disabled in firmware Giovanni Gherdovich
2021-05-13 9:24 ` Srinivas Pandruvada
2021-05-13 10:10 ` Giovanni Gherdovich
2021-05-13 11:03 ` Srinivas Pandruvada
2021-05-13 12:10 ` Giovanni Gherdovich
2021-05-13 13:20 ` [PATCH v2] cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode Giovanni Gherdovich
2021-05-14 15:31 ` Doug Smythies
2021-05-14 20:33 ` Giovanni Gherdovich
2021-05-14 22:12 ` Doug Smythies
2021-09-07 15:45 ` Doug Smythies
2021-09-07 16:01 ` Srinivas Pandruvada
2021-09-07 20:16 ` Doug Smythies
2021-09-08 2:04 ` Srinivas Pandruvada
2021-09-08 3:43 ` Doug Smythies [this message]
2021-09-14 18:41 ` Doug Smythies
2021-09-15 9:38 ` Srinivas Pandruvada
2021-05-15 2:58 ` Srinivas Pandruvada
2021-05-17 15:26 ` Rafael J. Wysocki
2021-05-18 11:33 ` Giovanni Gherdovich
2021-05-19 5:37 ` Doug Smythies
2021-05-18 12:34 ` [PATCH v3 1/2] " Giovanni Gherdovich
2021-05-18 12:34 ` [PATCH v3 2/2] cpufreq: intel_pstate: Add Cometlake " Giovanni Gherdovich
2021-05-21 16:49 ` [PATCH v3 1/2] cpufreq: intel_pstate: Add Icelake servers " Rafael J. Wysocki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAAYoRsVd4uU7sofcvYWd__evKJTf7HE5mi2ZVDjAYNYWXS3mzQ@mail.gmail.com \
--to=dsmythies@telus.net \
--cc=ggherdovich@suse.cz \
--cc=lenb@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rjw@rjwysocki.net \
--cc=srinivas.pandruvada@linux.intel.com \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).