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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org 2019=E5=B9=B47=E6=9C=8823=E6=97=A5(=E7=81=AB) 7:16 Rob Herring : > > On Mon, Jul 01, 2019 at 11:12:32PM +0900, Akinobu Mita wrote: > > Add thermal binding documentation for NVMe temperature sensor. > > > > Cc: Rob Herring > > Cc: Zhang Rui > > Cc: Eduardo Valentin > > Cc: Daniel Lezcano > > Cc: Keith Busch > > Cc: Jens Axboe > > Cc: Christoph Hellwig > > Cc: Sagi Grimberg > > Cc: Minwoo Im > > Cc: Kenneth Heitke > > Cc: Chaitanya Kulkarni > > Signed-off-by: Akinobu Mita > > --- > > * v5 > > - New patch > > > > Documentation/devicetree/bindings/thermal/nvme.txt | 56 ++++++++++++++= ++++++++ > > 1 file changed, 56 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/thermal/nvme.txt > > > > diff --git a/Documentation/devicetree/bindings/thermal/nvme.txt b/Docum= entation/devicetree/bindings/thermal/nvme.txt > > new file mode 100644 > > index 0000000..60b90de > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/thermal/nvme.txt > > @@ -0,0 +1,56 @@ > > +Binding for NVMe temperature sensor > > + > > +An NVMe controller reports up to nine temperature values in the SMART = / Health > > +log. > > + > > +Required properties: > > +- reg: A five-cell address encoded as (phys.hi phys.mid phys.lo size.h= i > > + size.lo). phys.hi should contain the device's BDF (Bus/Device/Functi= on) > > + as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be = zero. > > + See also Documentation/devicetree/bindings/pci/pci.txt > > + > > +- #thermal-sensor-cells: Must be 1. See ./thermal.txt for a descriptio= n. > > + In the thermal-sensors property, the sensor ID 0 for composite tempe= rature, > > + 1 through 8 for NVMe temperature sensor N. > > + > > +Example: > > + > > +&pcie0 { > > + ... > > + nvme: nvme@0,0 { > > + reg =3D <0x0000 0 0 0 0>; > > + #address-cells =3D <3>; > > + #size-cells =3D <2>; > > + > > + nvmetemp: nvmetemp { > > + reg =3D <0x0000 0 0 0 0>; /* DEVFN =3D 0x00 (0:0)= */ > > I'm not sure this is really valid PCI addressing as the parent has the > same address. > > > + #thermal-sensor-cells =3D <1>; > > Can't you just put this in the parent? Is this really a separate > addressable device from the parent? How about this? &pcie0 { ... pci-bridge@0 { reg =3D <0x00000 0 0 0 0>; #address-cells =3D <3>; #size-cells =3D <2>; nvme: nvme@0,0 { reg =3D <0x10000 0 0 0 0>; #thermal-sensor-cells =3D <1>; }; }; }; and &thermal_zones { ... thermal-sensors =3D <&nvme 0>; }; I tested this with the RockPro64 and edited arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts. $ lspci 00:00.0 PCI bridge: Fuzhou Rockchip Electronics Co., Ltd Device 0100 01:00.0 Non-Volatile memory controller: Micron/Crucial Technology Device 2263 (rev 03) $ lspci -tv -[0000:00]---00.0-[01]----00.0 Micron/Crucial Technology Device 2263