From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4FF8ECE598 for ; Tue, 15 Oct 2019 17:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C2AD72086A for ; Tue, 15 Oct 2019 17:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571161976; bh=BNIqSr8JLqhucOua3RO9pB9Y0snjy7Bkp6wmAXD+1So=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=YoJA+oqRG2qPA2AgmxszHbfx7VLZ0Hkk1DBrLa2SYsK0yCx1F8wjKtEE3hfvB/41z 7YHTiiSM2mIDQSGYVKK+r9g2EktDw23zmx1e8GTcnQm60keQKYOsMShhTJs8OcoHe6 8PhWByKYcEhC+69950/aBJQX2b5RfoHYc+ybvulQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729641AbfJORwz (ORCPT ); Tue, 15 Oct 2019 13:52:55 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:41078 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726192AbfJORwz (ORCPT ); Tue, 15 Oct 2019 13:52:55 -0400 Received: by mail-ot1-f67.google.com with SMTP id g13so17708036otp.8; Tue, 15 Oct 2019 10:52:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0awkrNAPcXWo+Wm8QfkD5O17YbDc9wlliWJjxDTQPl4=; b=A09rzlzGFg3ApjtfQolUx0XxOId8zdCTpVL2fhgTgcmL2qNYTJQ/QAPwTMzYOdBUGL hEyn0wRe4hq7oOBqHLpQcDSZtrfPx+RlkUI1S2q4eGu2Z+UI3zKXcs/hT9IImrtprId7 Rp4GFSbYrFYi/obgIQJuuqA+TwHAQLsdG28Yl5lwKDRjY6VSmop9DGTiWrVCFOnJnz2D p6om/04m9zyYrBpV2Y9BnwwCFUE4I1TXwmEED5T+jjItUEFgjFLW38cNPrrc3milLAdE f6/cM+AbqwfoRr9557VnAtLKkj6wY9UXpQe0bhpF8OGsOfP83L18r4z5SWWrrfefrWq5 VgXw== X-Gm-Message-State: APjAAAUkOenZSVnnQJsYj/klZkQKtFwSn0Lk8ZhvEDW/eOfP5RkASYBZ 2BvYMylx+pzZDHLvGfSBGj3CvRbmqqeKS23p+qA= X-Google-Smtp-Source: APXvYqy+z2640pLWXA/n52YLsdwhV9kHXEIfBefEfzEG0gR7AIhD1qLPwhn/HydFH/9RJQz2Qf4j1X31ihVGYH3jcuA= X-Received: by 2002:a05:6830:1e69:: with SMTP id m9mr1431970otr.262.1571161972801; Tue, 15 Oct 2019 10:52:52 -0700 (PDT) MIME-Version: 1.0 References: <20191014061355.29072-1-drake@endlessm.com> <20191014154322.GA190693@google.com> In-Reply-To: From: "Rafael J. Wysocki" Date: Tue, 15 Oct 2019 19:52:41 +0200 Message-ID: Subject: Re: [PATCH] PCI: increase D3 delay for AMD Ryzen5/7 XHCI controllers To: Daniel Drake Cc: Bjorn Helgaas , Linux PCI , "Wysocki, Rafael J" , Linux Upstreaming Team , Linux PM , Linux USB Mailing List , Mika Westerberg Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Tue, Oct 15, 2019 at 7:31 AM Daniel Drake wrote: > > On Mon, Oct 14, 2019 at 11:43 PM Bjorn Helgaas wrote: > > Can you tell if this is because the Ryzen7 XHCI controller is out of > > spec, or is the Linux PCI core missing some delay? If the latter, > > fixing the core might fix other devices as well. > > > > Mika has this patch: > > https://lore.kernel.org/r/20190821124519.71594-1-mika.westerberg@linux.intel.com > > for similar issues, but I think that patch fixes D3cold->D0 > > transitions, and your patch appears to be concerned with D3hot->D0 > > transitions. > > It's actually coming out of D3cold here, however what happens right > before this is that __pci_start_power_transition() calls > pci_platform_power_transition(D0) to leave D3cold state, then > pci_update_current_state() reads PMCSR and updates dev->current_state > to D3hot. Which pci_update_current_state() do you mean, exactly? Note that pci_platform_power_transition() itself contains one, which triggers after a successful change of the ACPI power state of the device (which should be the case here). Then, there is one in pci_power_up(), but before that the device's PMCSR is read from and written to in pci_raw_set_power_state(). It looks like the reads from it after the ACPI power state change are all successful, but the write isn't unless there is the delay between it and the former platform_pci_set_power_state(). > The 20ms delay for these XHCI controllers is needed precisely at this > point - after writing PMCSR to move to D0, and before reading it back > to check the result. > I tried moving the delay immediately before writing PMCSR, but that > doesn't work. Based on that, it seems like it's just a little out of > spec. That I agree with and the platform firmware doesn't compensate for that (which it could do, arguably).