From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Deepak Sharma <deepak.sharma@amd.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
"open list:SUSPEND TO RAM" <linux-pm@vger.kernel.org>,
"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
Date: Wed, 25 Aug 2021 20:07:40 +0200 [thread overview]
Message-ID: <CAJZ5v0jWX=H=aZ25PzHdH05bRJvtYbGHfyTgH_68k4kfYkZc5A@mail.gmail.com> (raw)
In-Reply-To: <20210819004305.20203-1-deepak.sharma@amd.com>
On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>
> AMD CPU which support C3 shares cache. Its not necessary to flush the
> caches in software before entering C3. This will cause performance drop
> for the cores which share some caches. ARB_DIS is not used with current
> AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
Optimize C3 entry on AMD CPUs", thanks!
> ---
> arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..62a5986d625a 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> */
> flags->bm_control = 0;
> }
> + if (c->x86_vendor == X86_VENDOR_AMD) {
> + /*
> + * For all AMD CPUs that support C3, caches should not be
> + * flushed by software while entering C3 type state. Set
> + * bm->check to 1 so that kernel doesn't need to execute
> + * cache flush operation.
> + */
> + flags->bm_check = 1;
> + /*
> + * In current AMD C state implementation ARB_DIS is no longer
> + * used. So set bm_control to zero to indicate ARB_DIS is not
> + * required while entering C3 type state.
> + */
> + flags->bm_control = 0;
> + }
> }
> EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-08-25 18:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 0:43 [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs Deepak Sharma
2021-08-25 18:07 ` Rafael J. Wysocki [this message]
2021-09-01 2:14 ` Deepak Sharma
2021-09-01 12:45 ` Rafael J. Wysocki
2021-09-22 3:50 ` Sharma, Deepak
2021-09-22 12:47 ` Rafael J. Wysocki
2021-09-24 5:42 ` Sharma, Deepak
2021-08-26 23:04 ` Thomas Gleixner
2021-09-01 2:10 ` Deepak Sharma
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAJZ5v0jWX=H=aZ25PzHdH05bRJvtYbGHfyTgH_68k4kfYkZc5A@mail.gmail.com' \
--to=rafael@kernel.org \
--cc=bp@alien8.de \
--cc=deepak.sharma@amd.com \
--cc=hpa@zytor.com \
--cc=len.brown@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=pavel@ucw.cz \
--cc=rjw@rjwysocki.net \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).