From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D18A0C432C3 for ; Thu, 21 Nov 2019 11:08:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A468420708 for ; Thu, 21 Nov 2019 11:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574334528; bh=2u05u5yvdV7LFv0UI+rCC49B8G8AxDejzvqEqBPmuUA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=wbEj8wVTsszqPdv/kxhYbRyRwWcTjtUi0evam4eg5pGUkWQIpbz0zVj0b/UVb0LW4 IGCuWxDypMIn8tEAVPegmwMmFenyVMEQmvHXj4CD+aCNHiy/GAq4SUp5UhXG7H3Jt3 GVeF69LotaZtanBxgCOeITH6zSFDNL8iNCr/Tctk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726698AbfKULIo (ORCPT ); Thu, 21 Nov 2019 06:08:44 -0500 Received: from mail-oi1-f194.google.com ([209.85.167.194]:45296 "EHLO mail-oi1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726343AbfKULIo (ORCPT ); Thu, 21 Nov 2019 06:08:44 -0500 Received: by mail-oi1-f194.google.com with SMTP id 14so2763941oir.12; Thu, 21 Nov 2019 03:08:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=J3Cy3tfrJiIUlL+D9Jr0kFLFrHhJQwh4Hdb4cuVFpa8=; b=t7izMp7L9m/mc+anZp95DTBPCpW00kdy7F08hqeD+CGRnja1NdfKf05/DPU3sk1eiX 95bD/kg33gi6jU3uBcDk8T63IlASiPOsto3+B4N0peXSJxpLgB0/Ewb7NMnsOLfZFSK5 SSs3K2dluw0O+F9ZkA4VJYo6HC7DtsniL9H3DEFngXLe/GkUUseyMdimjAYIjsN5y7Bl 3W6oBgNF3AxYL9aZ0i7aGzLEjOK+XPUPTem7vS5yqpSoy5lxELXCFEDhiz+BH7o1E9OB HtmzbsQ3O/V18GP0XVsdvuQ3daRYh5cqw5FGWNOaSPDZnlXBWI1AZHz5/1CqJmj1whu4 7e8A== X-Gm-Message-State: APjAAAUjdM2BHdEJLbRv1zRTm6QwvVBU72iAJiPpqiFoKLD53eAXVX/f 5/PfBJ3RA9uf3tazvyVQz2bbnpHLak01agRCSL4= X-Google-Smtp-Source: APXvYqxlqz4qNEUm0jTv4bAaBARGWgCnBqt/66UTTeVhGXft7P2C40EC7WWo0izyYaTsvvvl2QWLzkuMrcwnoaF2ur8= X-Received: by 2002:a05:6808:901:: with SMTP id w1mr7358488oih.57.1574334523139; Thu, 21 Nov 2019 03:08:43 -0800 (PST) MIME-Version: 1.0 References: <20191120115127.GD11621@lahna.fi.intel.com> <20191120120913.GE11621@lahna.fi.intel.com> <20191120151542.GH11621@lahna.fi.intel.com> <20191120155301.GL11621@lahna.fi.intel.com> <20191120162306.GM11621@lahna.fi.intel.com> <20191121101423.GQ11621@lahna.fi.intel.com> In-Reply-To: From: "Rafael J. Wysocki" Date: Thu, 21 Nov 2019 12:08:31 +0100 Message-ID: Subject: Re: [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges To: Mika Westerberg Cc: Karol Herbst , "Rafael J. Wysocki" , Bjorn Helgaas , LKML , Lyude Paul , "Rafael J . Wysocki" , Linux PCI , Linux PM , dri-devel , nouveau , Dave Airlie , Mario Limonciello Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Thu, Nov 21, 2019 at 12:03 PM Rafael J. Wysocki wrote: > > On Thu, Nov 21, 2019 at 11:14 AM Mika Westerberg > wrote: > > > > On Wed, Nov 20, 2019 at 10:36:31PM +0100, Karol Herbst wrote: > > > with the branch and patch applied: > > > https://gist.githubusercontent.com/karolherbst/03c4c8141b0fa292d781badfa186479e/raw/5c62640afbc57d6e69ea924c338bd2836e770d02/gistfile1.txt > > > > Thanks for testing. Too bad it did not help :( I suppose there is no > > change if you increase the delay to say 1s? > > Well, look at the original patch in this thread. > > What it does is to prevent the device (GPU in this particular case) > from going into a PCI low-power state before invoking AML to power it > down (the AML is still invoked after this patch AFAICS), so why would > that have anything to do with the delays? > > The only reason would be the AML running too early, but that doesn't > seem likely. IMO more likely is that the AML does something which > cannot be done to a device in a PCI low-power state. BTW, I'm wondering if anyone has tried to skip the AML instead of skipping the PCI PM in this case (as of 5.4-rc that would be a similar patch to skip the invocations of __pci_start/complete_power_transition() in pci_set_power_state() for the affected device).