From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93844C433FF for ; Tue, 13 Aug 2019 14:06:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 622182084D for ; Tue, 13 Aug 2019 14:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565705174; bh=O/fCUAPwaNaOOD9s9pkmueTj8itaAZFGU/uvEuU6kgc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=S88iGDydhVMoEBj20Uf6rLDXBFVrPj+fN8/JW9sTt4sJ/eQHz+Wm7Cks5Q3OVjP1c WEBebjvgMOZKa0zU5IL0743BHRmxmCji4UE4U4BYq2E+UnONcWC75buKMmGHitbDz9 /+u5T4wehh65SK01zEi/jiE2RAblA9H7llWncaT8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729546AbfHMOGN (ORCPT ); Tue, 13 Aug 2019 10:06:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:40262 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729438AbfHMOGN (ORCPT ); Tue, 13 Aug 2019 10:06:13 -0400 Received: from mail-qt1-f171.google.com (mail-qt1-f171.google.com [209.85.160.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 47CFA21744; Tue, 13 Aug 2019 14:06:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565705172; bh=O/fCUAPwaNaOOD9s9pkmueTj8itaAZFGU/uvEuU6kgc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=HpR0kTzh0L+1HCy1Trd3qsQrbjZn52IPfyQt3g5Y8VCr7jeQ4xAJGXgARJUR1xzUP klqdwHVZdgDWaLEyuO5irst9vm8D+yBfjbDxpDfpaPy5IwtXu8xDHljvjkBzTYqGfd 9qbk3phoAnuJjqVtWEPfHlqqv0nRh2ShRjc21dNs= Received: by mail-qt1-f171.google.com with SMTP id u34so7135061qte.2; Tue, 13 Aug 2019 07:06:12 -0700 (PDT) X-Gm-Message-State: APjAAAXWSLkjYplKz83m4/rtfRd83t72UPnqLi2i1FSIFIglA+ftSRwb TY/ddRLswAsRTdo5BU1McNXHPadD/MCzqie/jA== X-Google-Smtp-Source: APXvYqx3FMdHhwFr0AVbpQ+Lxot0AwypTnxtWq13JJOC5ylQw8YnX1DEfhh/V+OPrUwvGuTcbKUoILzXiL4zskKDN5g= X-Received: by 2002:aed:24f4:: with SMTP id u49mr6124643qtc.110.1565705171397; Tue, 13 Aug 2019 07:06:11 -0700 (PDT) MIME-Version: 1.0 References: <97b0bff95ddb85b06ef3d2f8079faa36562a956d.1565633880.git.leonard.crestez@nxp.com> In-Reply-To: From: Rob Herring Date: Tue, 13 Aug 2019 08:06:00 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/7] dt-bindings: devfreq: Add bindings for generic imx buses To: Leonard Crestez Cc: Stephen Boyd , MyungJoo Ham , Kyungmin Park , Shawn Guo , Michael Turquette , Chanwoo Choi , =?UTF-8?B?QXJ0dXIgxZp3aWdvxYQ=?= , Saravana Kannan , Krzysztof Kozlowski , Alexandre Bailon , Georgi Djakov , Aisheng Dong , Abel Vesa , Jacky Bai , Anson Huang , Fabio Estevam , Viresh Kumar , Will Deacon , Mark Rutland , "devicetree@vger.kernel.org" , "open list:THERMAL" , dl-linux-imx , Sascha Hauer , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Mon, Aug 12, 2019 at 7:32 PM Leonard Crestez wrote: > > On 8/12/2019 10:47 PM, Rob Herring wrote: > > On Mon, Aug 12, 2019 at 12:49 PM Leonard Crestez wrote: > > >> Add initial dt bindings for the interconnects inside i.MX chips. > >> Multiple external IPs are involved but SOC integration means the > >> software controllable interfaces are very similar. > >> > >> +description: | > >> + The i.MX SoC family has multiple buses for which clock frequency (and sometimes > >> + voltage) can be adjusted. > >> + > >> + Some of those buses expose register areas mentioned in the memory maps as GPV > >> + ("Global Programmers View") but not all. Access to this area might be denied for > >> + normal world. > >> + > >> + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris > >> + FlexNOC but DT bindings are specific to the integration of these bus > >> + interconnect IPs into imx SOCs. > > > > No need to use the interconnect binding? > > Separate RFC: https://patchwork.kernel.org/patch/11078673/ > > The interconnect is represented by a separate "virtual" node which might > not be OK. There was also a recent RFC from samsung which turns devfreq > nodes into interconnect providers: > https://patchwork.kernel.org/cover/11054417/ > > Is that preferable? Virtual nodes are not OK. > > >> +required: > >> + - compatible > >> + - clocks > > > > reg? > > This is deliberately optional: for some NICs the GPV register area is > not exposed in the memory map. This is unusual but an accurate > description of the hardware. Different h/w blocks should have different compatibles. GPV is an Arm thing and I'd expect FlexNOC to be different. > The current driver doesn't even attempt to map registers, it only > adjusts the clock. Irrelevant to the binding... > > >> +examples: > >> + - | > >> + #include > >> + noc: noc@32700000 { > >> + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; > > > > Doesn't match the schema. (Well, it does with 'contains', but > > fsl,imx8mm-noc is not documented.) > > I'm confused about how per-SOC compatible strings works with validation. > There is a rule that every SOC dtsi needs to add soc prefix to all > device nodes but of_device_id in driver code doesn't need to be updated. > > Without using "contains" on the "compatible" property then all > SOC-specific compatible strings would need to be mentioned in every yaml > files. Unless I'm missing something this means updating update every > binding file for each new SOC? Yes. The main exception is if various SoCs are just packaging, binning, or fuse differences. > > I guess it can be useful because it also validates the compatible > sequence itself. Right. Order matters. > > For this current example something like this seems to work: > > compatible: > oneOf: > - items: > - enum: > - fsl,imx8mm-nic > - fsl,imx8mq-nic > - const: fsl,imx8m-nic > - items: > - enum: > - fsl,imx8mm-noc > - fsl,imx8mq-noc > - const: fsl,imx8m-noc Looks correct. Rob