From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34A33C31E51 for ; Tue, 18 Jun 2019 11:56:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 06CC22070B for ; Tue, 18 Jun 2019 11:56:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mo7//ZZm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726275AbfFRL4u (ORCPT ); Tue, 18 Jun 2019 07:56:50 -0400 Received: from mail-ua1-f65.google.com ([209.85.222.65]:35184 "EHLO mail-ua1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726238AbfFRL4u (ORCPT ); Tue, 18 Jun 2019 07:56:50 -0400 Received: by mail-ua1-f65.google.com with SMTP id j21so7701uap.2 for ; Tue, 18 Jun 2019 04:56:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=piRTAebFx2FsROFm2zYcU51EDgaGKwKW/nF1spIt1sI=; b=mo7//ZZm5CR0ywBO0NeDMxPL71X9bJ2kFFt6G1IOlFmJ9ImsK53ikh7RHrkrW1cWy9 16iNhl4WpSQJUkAAbTw5KSaMvEgibjhRAeDdK923fBEpZYNAE20PQW/MvuGIVYjvr3Ly PGlsFZh24pJnk4p97S+BlQxGQ5YXakodnK0IFr1Bs6JN3UMFSZC7746dzX1JbDjIEtFl 5D7+lIshQcZUkRwA2eOa9jcmCy7QsLu2FCDfbDU8EzbL7pWXZADfQcDYZH0I6ds16AwR BbQa3geAipWWpwweByap68mRGunqBK9j3PxpS3+GHbGeM8wXH2f7fbKEAVQS0ldqg9eV IXAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=piRTAebFx2FsROFm2zYcU51EDgaGKwKW/nF1spIt1sI=; b=oJlyP5RBmehbpnBFKf58Y+DhQZ3HpFUOq5eet/dlrI7JrEKEBjaZe/qby5noeETzcf 3NDiP3jj5TcVhIZTLWzp8xpOZ/O1cn/rkv/9EI+rlUJfLd4PiX0zLJAsPgRU93ubJ7KB KHYnFQCswHTmzs6rwmMHJd55wTlAjCmScje0qJl2zlsRN2ACDWvSvuFXuePGs1xNm6BL 6gvyrV+mSlx92vwue7LLurqa//zhJLf28PzRQHHPpLbJVmPlvu7uDZfLOPgoqD8glXI9 U21PJB4BGIwXYaLb2NAiEPCzvP8WGYbPzuYzRuwq0FBYfG68kFQwvOWDEA7dnBADOxjI JU/A== X-Gm-Message-State: APjAAAXqyIeGnRN1N66zJA1hiKBpUkjDH26nlx71/vgpBWZI6ORSmilu x/lhc9NMBfot5kPYMXJwq+0+9botimbd26wom1dVDQ== X-Google-Smtp-Source: APXvYqxWE7NU+QUzDoR4u6I5eIyinKhKJ2E54DPFNLSdMDWyWFZV8l2G2R1evmkcZ1mRW3Z8CNDF2/bizF6JGRucbC8= X-Received: by 2002:a67:3254:: with SMTP id y81mr24197966vsy.34.1560859009184; Tue, 18 Jun 2019 04:56:49 -0700 (PDT) MIME-Version: 1.0 References: <20190513192300.653-1-ulf.hansson@linaro.org> <20190607154210.GJ15577@e107155-lin> <20190607193407.GB24059@builder> <20190610103225.GA26602@e107155-lin> <20190610171557.GA4560@redmoon> In-Reply-To: From: Ulf Hansson Date: Tue, 18 Jun 2019 13:56:13 +0200 Message-ID: Subject: Re: [PATCH 00/18] ARM/ARM64: Support hierarchical CPU arrangement for PSCI To: Lorenzo Pieralisi Cc: Sudeep Holla , Bjorn Andersson , "Rafael J. Wysocki" , Mark Rutland , Linux ARM , "Rafael J . Wysocki" , Daniel Lezcano , "Raju P . L . S . S . S . N" , Amit Kucheria , Stephen Boyd , Niklas Cassel , Tony Lindgren , Kevin Hilman , Lina Iyer , Viresh Kumar , Vincent Guittot , Geert Uytterhoeven , Souvik Chakravarty , Linux PM , linux-arm-msm , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Mon, 10 Jun 2019 at 20:57, Ulf Hansson wrote: > > On Mon, 10 Jun 2019 at 19:16, Lorenzo Pieralisi > wrote: > > > > On Mon, Jun 10, 2019 at 05:54:39PM +0200, Ulf Hansson wrote: > > > > [...] > > > > > My summary from the earlier ones, is that because the PSCI spec > > > includes support for OSI, we should also support it in the kernel (and > > > ATF). In a discussion offlist, Lorenzo agreed that it's okay to add, > > > without an apple to apple comparison. Maybe Lorenzo can fill in and > > > state this publicly, to save us all some time? > > > > The comparison should have been made before even requesting PSCI OSI > > mode changes to the specifications, so we have a chip on our shoulders > > anyway. > > > > We will enable PSCI OSI but that's not where the problem lies, enabling > > PSCI OSI from a firmware perspective should take 10 lines of code, > > not: > > Thanks for confirming! > > > > > drivers/firmware/psci/Makefile | 2 +- > > drivers/firmware/psci/psci.c | 219 ++++++++-- > > drivers/firmware/psci/psci.h | 29 ++ > > drivers/firmware/psci/psci_pm_domain.c | 403 ++++++++++++++++++ > > > > I have some concerns about these changes that I will state in the > > relevant patches. > > Most of the above changes isn't for solely for OSI, but to support a > hierarchical topology described in the PSCI DT layout. This is for > example needed when other resources shares the same power rail as the > CPU cluster. > > In other words, the series is orthogonal to whether OSI or PC mode is > used for PSCI, just to make that clear. BTW, this is what you > requested me to change into, a while ago. > > > > > > My final point in regards to the OSI mode support, it's a minor part > > > of the series. I don't see how that should hurt from a maintenance > > > point of view, or perhaps I am wrong? In any case, I offer my help > > > with review/maintenance in any form as you may see need/fit. > > > > I will go through the series but most of this code should move > > to core PM code, it has nothing to do with PSCI. > > I am looking forward to your review - and for sure, I am open to suggestions! > > > > > BTW, apologies for the delay, I was away. Lorenzo, a gentle ping. Kind regards Uffe