From: Rob Herring <robh@kernel.org>
To: vineetha.g.jaya.kumaran@intel.com
Cc: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de,
linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
wan.ahmad.zainie.wan.mohamad@intel.com,
andriy.shevchenko@intel.com
Subject: Re: [PATCH v2 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM
Date: Thu, 23 Jul 2020 11:47:01 -0600 [thread overview]
Message-ID: <20200723174701.GA584130@bogus> (raw)
In-Reply-To: <1595083628-20734-3-git-send-email-vineetha.g.jaya.kumaran@intel.com>
On Sat, Jul 18, 2020 at 10:47:08PM +0800, vineetha.g.jaya.kumaran@intel.com wrote:
> From: "Vineetha G. Jaya Kumaran" <vineetha.g.jaya.kumaran@intel.com>
>
> Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC.
>
> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
> ---
> .../devicetree/bindings/pwm/intel,keembay-pwm.yaml | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml
> new file mode 100644
> index 00000000..e9388a7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2020 Intel Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Keem Bay PWM Device Tree Bindings
> +
> +maintainers:
> + - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - intel,keembay-pwm
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#pwm-cells'
Add:
additionalProperties: false
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> +examples:
> + - |
> + #define KEEM_BAY_A53_GPIO
> +
> + pwm@203200a0 {
> + compatible = "intel,keembay-pwm";
> + reg = <0x203200a0 0xe8>;
> + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>;
> + #pwm-cells = <2>;
> + };
> --
> 1.9.1
>
next prev parent reply other threads:[~2020-07-23 17:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-18 14:47 [PATCH v2 0/2] Add PWM support for Intel Keem Bay SoC vineetha.g.jaya.kumaran
2020-07-18 14:47 ` [PATCH v2 1/2] pwm: Add PWM driver for Intel Keem Bay vineetha.g.jaya.kumaran
2020-07-18 20:41 ` kernel test robot
2020-07-18 21:17 ` kernel test robot
2020-07-21 9:13 ` Uwe Kleine-König
2020-07-27 5:12 ` G Jaya Kumaran, Vineetha
2020-07-29 6:20 ` G Jaya Kumaran, Vineetha
2020-07-18 14:47 ` [PATCH v2 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM vineetha.g.jaya.kumaran
2020-07-23 17:47 ` Rob Herring [this message]
2020-07-27 5:14 ` G Jaya Kumaran, Vineetha
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