From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-pwm@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>
Subject: [PATCH v4 1/4] dt-bindings: pwm: Add StarFive PWM module
Date: Thu, 1 Jun 2023 16:51:51 +0800 [thread overview]
Message-ID: <20230601085154.36938-2-william.qiu@starfivetech.com> (raw)
In-Reply-To: <20230601085154.36938-1-william.qiu@starfivetech.com>
Add documentation to describe StarFive Pulse Width Modulation
controller driver.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
new file mode 100644
index 000000000000..6f1937beb962
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 and JH7110 PWM controller
+
+maintainers:
+ - William Qiu <william.qiu@starfivetech.com>
+
+description:
+ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
+ binary signal with user-programmable low and high periods. Clock source for the
+ PWM can be either system clock or external clock. Each PWM timer block provides 8
+ PWM channels.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7100-pwm
+ - starfive,jh7110-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@12490000 {
+ compatible = "starfive,jh7100-pwm";
+ reg = <0x12490000 0x10000>;
+ clocks = <&clkgen 181>;
+ resets = <&rstgen 109>;
+ #pwm-cells = <3>;
+ };
--
2.34.1
next prev parent reply other threads:[~2023-06-01 8:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-01 8:51 [PATCH v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-06-01 8:51 ` William Qiu [this message]
2023-06-01 8:51 ` [PATCH v4 2/4] pwm: starfive: Add PWM " William Qiu
2023-06-01 8:51 ` [PATCH v4 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration William Qiu
2023-06-01 8:51 ` [PATCH v4 4/4] riscv: dts: starfive: jh7100: " William Qiu
2023-06-27 7:46 ` [PATCH v4 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-07-24 10:16 ` William Qiu
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