On Tue, Apr 20, 2021 at 11:51:18AM +0200, Uwe Kleine-König wrote:
> In the calculation of the register value determining the duty cycle the
> requested period is used instead of the actually implemented period which
> results in suboptimal settings.
> 
> The following example assumes an input clock of 133333333 Hz on one of
> the SoCs with 16 bit period.
> 
> When the following state is to be applied:
> 
>         .period = 414727681
>         .duty_cycle = 652806
> 
> the following register values used to be  calculated:
> 
>         PRES = 10
>         CPRD = 54000
>         CDTY = 53916
> 
> which yields an actual duty cycle of a bit more than 645120 ns.
> 
> The setting
> 
>         PRES = 10
>         CPRD = 54000
>         CDTY = 53915
> 
> however yields a duty of 652800 ns which is between the current result
> and the requested value and so is a better approximation.
> 
> The reason for this error is that for the calculation of CDTY the
> requested period was used instead of the actually implemented one.
> 
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
>  drivers/pwm/pwm-atmel.c | 23 ++++++++++++++++-------
>  1 file changed, 16 insertions(+), 7 deletions(-)

Applied, thanks.

Thierry