From: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
To: linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH rdma-core 14/14] Remove the old barrier macros
Date: Thu, 16 Feb 2017 12:23:09 -0700 [thread overview]
Message-ID: <1487272989-8215-15-git-send-email-jgunthorpe@obsidianresearch.com> (raw)
In-Reply-To: <1487272989-8215-1-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
Inline the required assembly directly into the new names. No change to
the asm.
Signed-off-by: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
---
util/udma_barrier.h | 195 +++++++++++++++++++++++++---------------------------
1 file changed, 94 insertions(+), 101 deletions(-)
diff --git a/util/udma_barrier.h b/util/udma_barrier.h
index f9b8291db20210..cc2718f33fc3a2 100644
--- a/util/udma_barrier.h
+++ b/util/udma_barrier.h
@@ -33,95 +33,6 @@
#ifndef __UTIL_UDMA_BARRIER_H
#define __UTIL_UDMA_BARRIER_H
-/*
- * Architecture-specific defines. Currently, an architecture is
- * required to implement the following operations:
- *
- * mb() - memory barrier. No loads or stores may be reordered across
- * this macro by either the compiler or the CPU.
- * rmb() - read memory barrier. No loads may be reordered across this
- * macro by either the compiler or the CPU.
- * wmb() - write memory barrier. No stores may be reordered across
- * this macro by either the compiler or the CPU.
- * wc_wmb() - flush write combine buffers. No write-combined writes
- * will be reordered across this macro by either the compiler or
- * the CPU.
- */
-
-#if defined(__i386__)
-
-#define mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
-#define rmb() mb()
-#define wmb() asm volatile("" ::: "memory")
-#define wc_wmb() mb()
-
-#elif defined(__x86_64__)
-
-/*
- * Only use lfence for mb() and rmb() because we don't care about
- * ordering against non-temporal stores (for now at least).
- */
-#define mb() asm volatile("lfence" ::: "memory")
-#define rmb() mb()
-#define wmb() asm volatile("" ::: "memory")
-#define wc_wmb() asm volatile("sfence" ::: "memory")
-
-#elif defined(__PPC64__)
-
-#define mb() asm volatile("sync" ::: "memory")
-#define rmb() asm volatile("lwsync" ::: "memory")
-#define wmb() mb()
-#define wc_wmb() wmb()
-
-#elif defined(__ia64__)
-
-#define mb() asm volatile("mf" ::: "memory")
-#define rmb() mb()
-#define wmb() mb()
-#define wc_wmb() asm volatile("fwb" ::: "memory")
-
-#elif defined(__PPC__)
-
-#define mb() asm volatile("sync" ::: "memory")
-#define rmb() mb()
-#define wmb() mb()
-#define wc_wmb() wmb()
-
-#elif defined(__sparc_v9__)
-
-#define mb() asm volatile("membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" ::: "memory")
-#define rmb() asm volatile("membar #LoadLoad" ::: "memory")
-#define wmb() asm volatile("membar #StoreStore" ::: "memory")
-#define wc_wmb() wmb()
-
-#elif defined(__sparc__)
-
-#define mb() asm volatile("" ::: "memory")
-#define rmb() mb()
-#define wmb() mb()
-#define wc_wmb() wmb()
-
-#elif defined(__s390x__)
-
-#define mb() { asm volatile("" : : : "memory"); } /* for s390x */
-#define rmb() mb() /* for s390x */
-#define wmb() mb() /* for s390x */
-#define wc_wmb() wmb() /* for s390x */
-
-#elif defined(__aarch64__)
-
-/* Perhaps dmb would be sufficient? Let us be conservative for now. */
-#define mb() { asm volatile("dsb sy" ::: "memory"); }
-#define rmb() { asm volatile("dsb ld" ::: "memory"); }
-#define wmb() { asm volatile("dsb st" ::: "memory"); }
-#define wc_wmb() wmb()
-
-#else
-
-#error No architecture specific memory barrier defines found!
-
-#endif
-
/* Barriers for DMA.
These barriers are expliclty only for use with user DMA operations. If you
@@ -143,6 +54,10 @@
The ordering guarentee is always stated between those two streams. Eg what
happens if a MemRd TLP is sent in via PCI-E relative to a CPU WRITE to the
same memory location.
+
+ The providers have a very regular and predictable use of these barriers,
+ to make things very clear each narrow use is given a name and the proper
+ name should be used in the provider as a form of documentation.
*/
/* Ensure that the device's view of memory matches the CPU's view of memory.
@@ -163,7 +78,25 @@
memory types or non-temporal stores are required to use SFENCE in their own
code prior to calling verbs to start a DMA.
*/
-#define udma_to_device_barrier() wmb()
+#if defined(__i386__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#elif defined(__x86_64__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#elif defined(__PPC64__)
+#define udma_to_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__PPC__)
+#define udma_to_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define udma_to_device_barrier() asm volatile("mf" ::: "memory")
+#elif defined(__sparc_v9__)
+#define udma_to_device_barrier() asm volatile("membar #StoreStore" ::: "memory")
+#elif defined(__aarch64__)
+#define wmb() asm volatile("dsb st" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define udma_to_device_barrier() asm volatile("" ::: "memory")
+#else
+#error No architecture specific memory barrier defines found!
+#endif
/* Ensure that all ordered stores from the device are observable from the
CPU. This only makes sense after something that observes an ordered store
@@ -177,7 +110,25 @@
that is a DMA target, to ensure that the following reads see the
data written before the MemWr TLP that set the valid bit.
*/
-#define udma_from_device_barrier() rmb()
+#if defined(__i386__)
+#define udma_from_device_barrier() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
+#elif defined(__x86_64__)
+#define udma_from_device_barrier() asm volatile("lfence" ::: "memory")
+#elif defined(__PPC64__)
+#define udma_from_device_barrier() asm volatile("lwsync" ::: "memory")
+#elif defined(__PPC__)
+#define udma_from_device_barrier() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define udma_from_device_barrier() asm volatile("mf" ::: "memory")
+#elif defined(__sparc_v9__)
+#define udma_from_device_barrier() asm volatile("membar #LoadLoad" ::: "memory")
+#elif defined(__aarch64__)
+#define udma_from_device_barrier() asm volatile("dsb ld" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define udma_from_device_barrier() asm volatile("" ::: "memory")
+#else
+#error No architecture specific memory barrier defines found!
+#endif
/* Order writes to CPU memory so that a DMA device cannot view writes after
the barrier without also seeing all writes before the barrier. This does
@@ -198,24 +149,66 @@
udma_ordering_write_barrier(); // Guarantee WQE written in order
wqe->valid = 1;
*/
-#define udma_ordering_write_barrier() wmb()
+#define udma_ordering_write_barrier() udma_to_device_barrier()
-/* Promptly flush writes, possibly in a write buffer, to MMIO backed memory.
- This is not required to have any effect on CPU memory. If done while
- holding a lock then the ordering of MMIO writes across CPUs must be
- guarenteed to follow the natural ordering implied by the lock.
+/* Promptly flush writes to MMIO Write Cominbing memory.
+ This should be used after a write to WC memory. This is both a barrier
+ and a hint to the CPU to flush any buffers to reduce latency to TLP
+ generation.
+
+ This is not required to have any effect on CPU memory.
+
+ If done while holding a lock then the ordering of MMIO writes across CPUs
+ must be guarenteed to follow the natural ordering implied by the lock.
This must also act as a barrier that prevents write combining, eg
*wc_mem = 1;
mmio_flush_writes();
*wc_mem = 2;
- Must always produce two MemWr TLPs, the '2' cannot be combined with and
- supress the '1'.
+ Must always produce two MemWr TLPs, '1' and '2'. Without the barrier
+ the CPU is allowed to produce a single TLP '2'.
+
+ Note that there is no order guarentee for writes to WC memory without
+ barriers.
+
+ This is intended to be used in conjunction with WC memory to generate large
+ PCI-E MemWr TLPs from the CPU.
+*/
+#if defined(__i386__)
+#define mmio_flush_writes() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
+#elif defined(__x86_64__)
+#define mmio_flush_writes() asm volatile("sfence" ::: "memory")
+#elif defined(__PPC64__)
+#define mmio_flush_writes() asm volatile("sync" ::: "memory")
+#elif defined(__PPC__)
+#define mmio_flush_writes() asm volatile("sync" ::: "memory")
+#elif defined(__ia64__)
+#define mmio_flush_writes() asm volatile("fwb" ::: "memory")
+#elif defined(__sparc_v9__)
+#define mmio_flush_writes() asm volatile("membar #StoreStore" ::: "memory")
+#elif defined(__aarch64__)
+#define mmio_flush_writes() asm volatile("dsb st" ::: "memory");
+#elif defined(__sparc__) || defined(__s390x__)
+#define mmio_flush_writes() asm volatile("" ::: "memory")
+#error No architecture specific memory barrier defines found!
+#endif
+
+/* Prevent WC writes from being re-ordered relative to other MMIO
+ writes. This should be used before a write to WC memory.
+
+ This must act as a barrier to prevent write re-ordering from different
+ memory types:
+ *mmio_mem = 1;
+ mmio_flush_writes();
+ *wc_mem = 2;
+ Must always produce a TLP '1' followed by '2'.
+
+ This barrier implies udma_to_device_barrier()
- This is intended to be used in conjunction with write combining memory
- to generate large PCI-E MemWr TLPs from the CPU.
+ This is intended to be used in conjunction with WC memory to generate large
+ PCI-E MemWr TLPs from the CPU.
*/
-#define mmio_flush_writes() wc_wmb()
+#define mmio_wc_start() mmio_flush_writes()
/* Keep MMIO writes in order.
Currently we lack writel macros that universally guarentee MMIO
--
2.7.4
--
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next prev parent reply other threads:[~2017-02-16 19:23 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-16 19:22 [PATCH rdma-core 00/14] Revise the DMA barrier macros in ibverbs Jason Gunthorpe
[not found] ` <1487272989-8215-1-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-16 19:22 ` [PATCH rdma-core 01/14] mlx5: Use stdatomic for the in_use barrier Jason Gunthorpe
2017-02-16 19:22 ` [PATCH rdma-core 02/14] Provide new names for the CPU barriers related to DMA Jason Gunthorpe
[not found] ` <1487272989-8215-3-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-16 22:07 ` Steve Wise
2017-02-17 16:37 ` Jason Gunthorpe
2017-02-16 19:22 ` [PATCH rdma-core 03/14] cxgb3: Update to use new udma write barriers Jason Gunthorpe
[not found] ` <1487272989-8215-4-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-16 21:20 ` Steve Wise
2017-02-16 21:45 ` Jason Gunthorpe
[not found] ` <20170216214527.GA13616-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-16 22:01 ` Steve Wise
2017-02-16 19:22 ` [PATCH rdma-core 04/14] cxgb4: " Jason Gunthorpe
[not found] ` <1487272989-8215-5-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-17 20:16 ` Steve Wise
2017-02-16 19:23 ` [PATCH rdma-core 05/14] hns: " Jason Gunthorpe
2017-02-16 19:23 ` [PATCH rdma-core 06/14] i40iw: Get rid of unique barrier macros Jason Gunthorpe
[not found] ` <1487272989-8215-7-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-01 17:29 ` Shiraz Saleem
[not found] ` <20170301172920.GA11340-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-01 17:55 ` Jason Gunthorpe
[not found] ` <20170301175521.GB14791-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-01 22:14 ` Shiraz Saleem
[not found] ` <20170301221420.GA18548-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-01 23:05 ` Jason Gunthorpe
[not found] ` <20170301230506.GB2820-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-03 21:45 ` Shiraz Saleem
[not found] ` <20170303214514.GA12996-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-03 22:22 ` Jason Gunthorpe
[not found] ` <20170303222244.GA678-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-06 19:16 ` Shiraz Saleem
[not found] ` <20170306191631.GB34252-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-06 19:40 ` Jason Gunthorpe
[not found] ` <20170306194052.GB31672-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-07 22:46 ` Shiraz Saleem
[not found] ` <20170307224622.GA45028-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-07 22:50 ` Jason Gunthorpe
[not found] ` <20170307225027.GA20858-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-07 23:01 ` Shiraz Saleem
[not found] ` <20170307230121.GA52428-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-07 23:11 ` Jason Gunthorpe
[not found] ` <20170307231145.GB20858-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-07 23:23 ` Shiraz Saleem
2017-03-06 18:18 ` Shiraz Saleem
[not found] ` <20170306181808.GA34252-GOXS9JX10wfOxmVO0tvppfooFf0ArEBIu+b9c/7xato@public.gmane.org>
2017-03-06 19:07 ` Jason Gunthorpe
[not found] ` <20170306190751.GA30663-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-07 23:16 ` Shiraz Saleem
2017-02-16 19:23 ` [PATCH rdma-core 07/14] mlx4: Update to use new udma write barriers Jason Gunthorpe
[not found] ` <1487272989-8215-8-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-20 17:46 ` Yishai Hadas
[not found] ` <206559e5-0488-f6d5-c4ec-bf560e0c3ba6-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-02-21 18:14 ` Jason Gunthorpe
[not found] ` <20170221181407.GA13138-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-06 14:57 ` Yishai Hadas
[not found] ` <45d2b7da-9ad6-6b37-d0b2-00f7807966b4-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-03-06 17:31 ` Jason Gunthorpe
[not found] ` <20170306173139.GA11805-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-07 16:44 ` Yishai Hadas
[not found] ` <55bcc87e-b059-65df-8079-100120865ffb-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-03-07 19:18 ` Jason Gunthorpe
[not found] ` <20170307191824.GD2228-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-08 21:27 ` Yishai Hadas
[not found] ` <6571cf34-63b9-7b83-ddb0-9279e7e20fa9-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-03-08 21:56 ` Jason Gunthorpe
[not found] ` <20170308215609.GB4109-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-09 15:42 ` Yishai Hadas
[not found] ` <4dcf0cea-3652-0df2-9d98-74e258e6170a-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-03-09 17:03 ` Jason Gunthorpe
[not found] ` <20170309170320.GA12694-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-13 15:17 ` Yishai Hadas
2017-02-16 19:23 ` [PATCH rdma-core 08/14] mlx5: " Jason Gunthorpe
[not found] ` <1487272989-8215-9-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-27 10:56 ` Yishai Hadas
[not found] ` <d5921636-1911-5588-8c59-620066bca01a-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-02-27 18:00 ` Jason Gunthorpe
[not found] ` <20170227180009.GL5891-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-28 16:02 ` Yishai Hadas
[not found] ` <2969cce4-8b51-8fcf-f099-2b42a6d40a9c-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-02-28 17:06 ` Jason Gunthorpe
[not found] ` <20170228170658.GA17995-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-02 9:34 ` Yishai Hadas
[not found] ` <24bf0e37-e032-0862-c5b9-b5a40fcfb343-LDSdmyG8hGV8YrgS2mwiifqBs+8SCbDb@public.gmane.org>
2017-03-02 17:12 ` Jason Gunthorpe
[not found] ` <20170302171210.GA8595-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-06 14:19 ` Yishai Hadas
2017-02-16 19:23 ` [PATCH rdma-core 09/14] nes: " Jason Gunthorpe
2017-02-16 19:23 ` [PATCH rdma-core 10/14] mthca: Update to use new mmio " Jason Gunthorpe
2017-02-16 19:23 ` [PATCH rdma-core 11/14] ocrdma: Update to use new udma " Jason Gunthorpe
[not found] ` <1487272989-8215-12-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-18 16:21 ` Devesh Sharma
2017-02-16 19:23 ` [PATCH rdma-core 12/14] qedr: " Jason Gunthorpe
[not found] ` <1487272989-8215-13-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-23 13:49 ` Amrani, Ram
[not found] ` <SN1PR07MB2207DE206738E6DD8511CEA1F8530-mikhvbZlbf8TSoR2DauN2+FPX92sqiQdvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-02-23 17:30 ` Jason Gunthorpe
[not found] ` <20170223173047.GC6688-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-24 10:01 ` Amrani, Ram
2017-02-16 19:23 ` [PATCH rdma-core 13/14] vmw_pvrdma: " Jason Gunthorpe
[not found] ` <1487272989-8215-14-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-17 18:05 ` Adit Ranadive
2017-02-16 19:23 ` Jason Gunthorpe [this message]
[not found] ` <1487272989-8215-15-git-send-email-jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-02-23 13:33 ` [PATCH rdma-core 14/14] Remove the old barrier macros Amrani, Ram
[not found] ` <SN1PR07MB22070A48ACD50848267A5AD8F8530-mikhvbZlbf8TSoR2DauN2+FPX92sqiQdvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-02-23 16:59 ` Jason Gunthorpe
2017-02-28 16:00 ` [PATCH rdma-core 00/14] Revise the DMA barrier macros in ibverbs Doug Ledford
[not found] ` <1488297611.86943.215.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2017-02-28 16:38 ` Majd Dibbiny
[not found] ` <C6384D48-FC47-4046-8025-462E1CB02A34-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
2017-02-28 17:47 ` Doug Ledford
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