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From: Yishai Hadas <yishaih@mellanox.com>
To: linux-rdma@vger.kernel.org
Cc: jgg@mellanox.com, dledford@redhat.com, yishaih@mellanox.com,
	maorg@mellanox.com, michaelgur@mellanox.com,
	Edward Srouji <edwards@mellanox.com>
Subject: [PATCH rdma-core 7/7] tests: Add relaxed ordering access test
Date: Thu,  9 Jan 2020 16:04:36 +0200
Message-ID: <1578578676-752-8-git-send-email-yishaih@mellanox.com> (raw)
In-Reply-To: <1578578676-752-1-git-send-email-yishaih@mellanox.com>

From: Michael Guralnik <michaelgur@mellanox.com>

Test traffic with MRs with relaxed ordering access set.

Signed-off-by: Michael Guralnik <michaelgur@mellanox.com>
Signed-off-by: Edward Srouji <edwards@mellanox.com>
---
 tests/CMakeLists.txt           |  5 ++--
 tests/test_relaxed_ordering.py | 55 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 2 deletions(-)
 create mode 100644 tests/test_relaxed_ordering.py

diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 6d70242..cacfc52 100755
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -10,11 +10,12 @@ rdma_python_test(tests
   test_cqex.py
   test_device.py
   test_mr.py
-  test_pd.py
-  test_qp.py
   test_odp.py
+  test_pd.py
   test_parent_domain.py
+  test_qp.py
   test_rdmacm.py
+  test_relaxed_ordering.py
   utils.py
   )
 
diff --git a/tests/test_relaxed_ordering.py b/tests/test_relaxed_ordering.py
new file mode 100644
index 0000000..27af992
--- /dev/null
+++ b/tests/test_relaxed_ordering.py
@@ -0,0 +1,55 @@
+from tests.base import RCResources, UDResources, XRCResources
+from tests.utils import traffic, xrc_traffic
+from tests.base import RDMATestCase
+from pyverbs.mr import MR
+import pyverbs.enums as e
+
+
+class RoUD(UDResources):
+    def create_mr(self):
+        self.mr = MR(self.pd, self.msg_size + self.GRH_SIZE,
+                     e.IBV_ACCESS_LOCAL_WRITE | e.IBV_ACCESS_RELAXED_ORDERING)
+
+
+class RoRC(RCResources):
+    def create_mr(self):
+        self.mr = MR(self.pd, self.msg_size,
+                     e.IBV_ACCESS_LOCAL_WRITE | e.IBV_ACCESS_RELAXED_ORDERING)
+
+
+class RoXRC(XRCResources):
+    def create_mr(self):
+        self.mr = MR(self.pd, self.msg_size,
+                     e.IBV_ACCESS_LOCAL_WRITE | e.IBV_ACCESS_RELAXED_ORDERING)
+
+
+class RoTestCase(RDMATestCase):
+    def setUp(self):
+        super(RoTestCase, self).setUp()
+        self.iters = 100
+        self.qp_dict = {'rc': RoRC, 'ud': RoUD, 'xrc': RoXRC}
+
+    def create_players(self, qp_type):
+        client = self.qp_dict[qp_type](self.dev_name, self.ib_port,
+                                       self.gid_index)
+        server = self.qp_dict[qp_type](self.dev_name, self.ib_port,
+                                       self.gid_index)
+        if qp_type == 'xrc':
+            client.pre_run(server.psns, server.qps_num)
+            server.pre_run(client.psns, client.qps_num)
+        else:
+            client.pre_run(server.psn, server.qpn)
+            server.pre_run(client.psn, client.qpn)
+        return client, server
+
+    def test_ro_rc_traffic(self):
+        client, server = self.create_players('rc')
+        traffic(client, server, self.iters, self.gid_index, self.ib_port)
+
+    def test_ro_ud_traffic(self):
+        client, server = self.create_players('ud')
+        traffic(client, server, self.iters, self.gid_index, self.ib_port)
+
+    def test_ro_xrc_traffic(self):
+        client, server = self.create_players('xrc')
+        xrc_traffic(client, server)
-- 
1.8.3.1


  parent reply index

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-09 14:04 [PATCH rdma-core 0/7] verbs: Relaxed ordering memory regions Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 1/7] Update kernel headers Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 2/7] verbs: Move free_context from verbs_device_ops to verbs_context_ops Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 3/7] verbs: Move alloc_context to ioctl Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 4/7] verbs: Relaxed ordering memory regions Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 5/7] mlx5: Add optional access flags range to DM Yishai Hadas
2020-01-09 14:04 ` [PATCH rdma-core 6/7] pyverbs: Add relaxed ordering access flag Yishai Hadas
2020-01-09 14:04 ` Yishai Hadas [this message]
2020-01-22  9:50 ` [PATCH rdma-core 0/7] verbs: Relaxed ordering memory regions Yishai Hadas

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