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Miller" , Dennis Dalessandro , Devesh Sharma , Faisal Latif , "Jack Wang" , Jakub Kicinski , "J. Bruce Fields" , Jens Axboe , Karsten Graul , Keith Busch , Lijun Ou , , , , , , , Max Gurtovoy , "Md. Haris Iqbal" , Michael Guralnik , Michal Kalderon , Mike Marciniszyn , Naresh Kumar PBS , , Potnuri Bharat Teja , , Sagi Grimberg , , Santosh Shilimkar , Selvin Xavier , Shiraz Saleem , Somnath Kotur , Sriharsha Basavapatna , Steve French , "Trond Myklebust" , VMware PV-Drivers , Weihang Li , Yishai Hadas , Zhu Yanjun References: <20210405052404.213889-1-leon@kernel.org> <20210406023738.GB80908@dhcp-128-72.nay.redhat.com> <20210406115323.GI7405@nvidia.com> From: Max Gurtovoy Message-ID: <1ac705a6-0504-fa6e-4d4d-5256b40c363d@nvidia.com> Date: Sun, 11 Apr 2021 13:09:03 +0300 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.1 MIME-Version: 1.0 In-Reply-To: <20210406115323.GI7405@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f19b0805-f25e-448a-a41a-08d8fcd1df33 X-MS-TrafficTypeDiagnostic: DM4PR12MB5229: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: itazsxFFFurAQjJ+0VnFXXXyGDMTFZuxOv2X6p5cBARmhMA3t1R5Kwe1yptq8GKTm6CeVwmGv3rlAMTeDPPI5JBXlPyHMHjhA8wjy0Vp8eFyF/ZhMPTy0LiCcIge0FPI9Ze5hzl+SaLDI6Y5jriciZlvHfzuzMQPm+KG5UpeCrzWIshfklsYQ7QmIkclJyFdYNS02NiQ+//3KARZ0oc1NAensmkh0zQgrvgXE2kUksWudp2RDKLJeZV2XFtdYJFcUOmlrHwTth++XXTtsQEbXWohZyPv4F0qLtcZjF+MtCMdyg8JgqnUdNOInrYSA+QIwkPltvcJFWQOW80ic7QAOZ64Z/b/b/uGWLRZX52DOdWJlAc/sOMVEDt2trKKWIHNGYDxedkQhtUI7UrVhlA7olVui8ASc0mTews0kPm171JEXso8+1i2wU1pxlI8N2PAWQDtpr5jjqiOKJbIogeRfkpkUouTrSgpAx7O/xWKgQxq4BWYUvERUQDEu9b0HwqYou7FVA6lIS0yxeS9eOSGRiVrhoI3CoH+Da2hk9IeEi7ZvGIq/IbY5ik6Q1mPgRZMT5/Ji2zb1n4LySXBLUVWGE3rcijzEciQ9fqW3bItnhttnvSprYPNdd8ZTGNT8L89BMwfofuP/LovKUubNZ6c0NZ4u04T7I7l7yFY4h6Tt5q6SyYJdMBUb3xFFNrJK1ckwzuadyt4Lw0jtmr8TmjEdkGNaX6+q8BJfTgJfWUw/79AKjVgdLUESE08h3JLh8tLMcjPSBbAvaUEH8BIQXwJdg== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(39860400002)(346002)(136003)(376002)(396003)(46966006)(36840700001)(31696002)(36756003)(86362001)(70586007)(82310400003)(53546011)(83380400001)(31686004)(70206006)(7636003)(47076005)(336012)(356005)(7416002)(7406005)(110136005)(54906003)(26005)(36906005)(16576012)(16526019)(8676002)(316002)(4326008)(186003)(426003)(2616005)(8936002)(478600001)(5660300002)(6666004)(966005)(2906002)(82740400003)(36860700001)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2021 10:09:19.4933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f19b0805-f25e-448a-a41a-08d8fcd1df33 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5229 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On 4/6/2021 2:53 PM, Jason Gunthorpe wrote: > On Tue, Apr 06, 2021 at 08:09:43AM +0300, Leon Romanovsky wrote: >> On Tue, Apr 06, 2021 at 10:37:38AM +0800, Honggang LI wrote: >>> On Mon, Apr 05, 2021 at 08:23:54AM +0300, Leon Romanovsky wrote: >>>> From: Leon Romanovsky >>>> >>>> From Avihai, >>>> >>>> Relaxed Ordering is a PCIe mechanism that relaxes the strict ordering >>>> imposed on PCI transactions, and thus, can improve performance. >>>> >>>> Until now, relaxed ordering could be set only by user space applications >>>> for user MRs. The following patch series enables relaxed ordering for the >>>> kernel ULPs as well. Relaxed ordering is an optional capability, and as >>>> such, it is ignored by vendors that don't support it. >>>> >>>> The following test results show the performance improvement achieved >>> Did you test this patchset with CPU does not support relaxed ordering? >> I don't think so, the CPUs that don't support RO are Intel's fourth/fifth-generation >> and they are not interesting from performance point of view. >> >>> We observed significantly performance degradation when run perftest with >>> relaxed ordering enabled over old CPU. >>> >>> https://github.com/linux-rdma/perftest/issues/116 >> The perftest is slightly different, but you pointed to the valid point. >> We forgot to call pcie_relaxed_ordering_enabled() before setting RO bit >> and arguably this was needed to be done in perftest too. > No, the PCI device should not have the RO bit set in this situation. > It is something mlx5_core needs to do. We can't push this into > applications. pcie_relaxed_ordering_enabled is called in drivers/net/ethernet/mellanox/mlx5/core/en_common.c so probably need to move it to mlx5_core in this series. > > There should be no performance difference from asking for > IBV_ACCESS_RELAXED_ORDERING when RO is disabled at the PCI config and > not asking for it at all. > > Either the platform has working relaxed ordering that gives a > performance gain and the RO config spec bit should be set, or it > doesn't and the bit should be clear. is this the case today ? > > This is not something to decide in userspace, or in RDMA. At worst it > becomes another platform specific PCI tunable people have to set. > > I thought the old haswell systems were quirked to disable RO globally > anyhow? > > Jason