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received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: p/+QHhwvw28DULJWxKXCbn5/+cGEY2jewUi9KFhF9tESCWt0JW3Tu5/2WGMt8oGfVNSxrzPIVPcMOa6k7YLRcB+cLZyBu84xl2ObunzJYQl0FYTIlwlpEE8HfxfyYdyHfflMj25TE5M7+vI4ZKYpdpGXm8ENNrjhUJcNGIiRLhNOUN4n3GAPgmyA7PwuVvyohDUZKKD95BqC/6yoNTq4RRfCp0ImXElV7819LAL+xFAgKgsj9iJtBQNKEWpKy3J4NiHI6JKUSDLdQiU99tkZlrt54sm6PgphVdH2P/QvHNNSGnEnqf0y1LJMxIaynnnawoPz0L+Ixv7+FK3mixD8Fzm/CaR3FXuTA1RQhmR8AYVcLatWGLc00o3HP/Q4DjRgyzOqZcGD/EaIW8QpCh6a4x02GuNoAp5z36fTzs7Vj8I5TA7y8lb+VflI/QzLbGGq Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: c63636b1-a8ab-487c-e827-08d76e081e73 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2019 22:22:24.7459 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xos1X8N6yKaxH8P2FO2+1ShL+5ScU7KY8Qtd299BqQ13xFK/6L8PIWvuwXcsVmE2Ar226daae9DFktynQJ1AjA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR05MB5341 Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Eran Ben Elisha On load, Driver caches MCAM (Management Capabilities Mask Register) registers. In addition to the only MCAM register group (0) the driver already reads, here we add support for reading groups 1 and 2. Signed-off-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 15 +++++++++------ include/linux/mlx5/device.h | 14 +++++++++++++- include/linux/mlx5/driver.h | 2 +- 3 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/eth= ernet/mellanox/mlx5/core/fw.c index a19790dee7b2..1723229a9259 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -131,11 +131,11 @@ static int mlx5_get_pcam_reg(struct mlx5_core_dev *de= v) MLX5_PCAM_REGS_5000_TO_507F); } =20 -static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) +static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev, + enum mlx5_mcam_reg_groups group) { - return mlx5_query_mcam_reg(dev, dev->caps.mcam, - MLX5_MCAM_FEATURE_ENHANCED_FEATURES, - MLX5_MCAM_REGS_FIRST_128); + return mlx5_query_mcam_reg(dev, dev->caps.mcam[group], + MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group); } =20 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev) @@ -221,8 +221,11 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) if (MLX5_CAP_GEN(dev, pcam_reg)) mlx5_get_pcam_reg(dev); =20 - if (MLX5_CAP_GEN(dev, mcam_reg)) - mlx5_get_mcam_reg(dev); + if (MLX5_CAP_GEN(dev, mcam_reg)) { + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF); + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); + } =20 if (MLX5_CAP_GEN(dev, qcam_reg)) mlx5_get_qcam_reg(dev); diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index cc1c230f10ee..1715252b2f74 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1120,6 +1120,9 @@ enum mlx5_pcam_feature_groups { =20 enum mlx5_mcam_reg_groups { MLX5_MCAM_REGS_FIRST_128 =3D 0x0, + MLX5_MCAM_REGS_0x9080_0x90FF =3D 0x1, + MLX5_MCAM_REGS_0x9100_0x917F =3D 0x2, + MLX5_MCAM_REGS_NUM =3D 0x3, }; =20 enum mlx5_mcam_feature_groups { @@ -1268,7 +1271,16 @@ enum mlx5_qcam_feature_groups { MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_= to_507f.reg) =20 #define MLX5_CAP_MCAM_REG(mdev, reg) \ - MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs= .reg) + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ + mng_access_reg_cap_mask.access_regs.reg) + +#define MLX5_CAP_MCAM_REG1(mdev, reg) \ + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \ + mng_access_reg_cap_mask.access_regs1.reg) + +#define MLX5_CAP_MCAM_REG2(mdev, reg) \ + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ + mng_access_reg_cap_mask.access_regs2.reg) =20 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_featu= res.fld) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1884513aac90..462c67e2dc13 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -686,7 +686,7 @@ struct mlx5_core_dev { u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; - u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; + u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; u8 embedded_cpu; --=20 2.21.0