* [PATCH mlx5-next 1/5] net/mlx5: Add structures layout for new MCAM access reg groups
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
@ 2019-11-20 22:22 ` Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 2/5] net/mlx5: Read MCAM register groups 1 and 2 Saeed Mahameed
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-20 22:22 UTC (permalink / raw)
To: Saeed Mahameed, Leon Romanovsky; +Cc: netdev, linux-rdma, Eran Ben Elisha
From: Eran Ben Elisha <eranbe@mellanox.com>
MCAM has 3 access_reg_groups (0-2). Defines data structures in order to
read and parse access_reg_groups #1 and #2.
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
include/linux/mlx5/mlx5_ifc.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index c0bfb1d90dd2..97acbe8cebf8 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -8817,6 +8817,28 @@ struct mlx5_ifc_mcam_access_reg_bits {
u8 regs_31_to_0[0x20];
};
+struct mlx5_ifc_mcam_access_reg_bits1 {
+ u8 regs_127_to_96[0x20];
+
+ u8 regs_95_to_64[0x20];
+
+ u8 regs_63_to_32[0x20];
+
+ u8 regs_31_to_0[0x20];
+};
+
+struct mlx5_ifc_mcam_access_reg_bits2 {
+ u8 regs_127_to_99[0x1d];
+ u8 mirc[0x1];
+ u8 regs_97_to_96[0x2];
+
+ u8 regs_95_to_64[0x20];
+
+ u8 regs_63_to_32[0x20];
+
+ u8 regs_31_to_0[0x20];
+};
+
struct mlx5_ifc_mcam_reg_bits {
u8 reserved_at_0[0x8];
u8 feature_group[0x8];
@@ -8827,6 +8849,8 @@ struct mlx5_ifc_mcam_reg_bits {
union {
struct mlx5_ifc_mcam_access_reg_bits access_regs;
+ struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
+ struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
u8 reserved_at_0[0x80];
} mng_access_reg_cap_mask;
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH mlx5-next 2/5] net/mlx5: Read MCAM register groups 1 and 2
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 1/5] net/mlx5: Add structures layout for new MCAM access reg groups Saeed Mahameed
@ 2019-11-20 22:22 ` Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 3/5] net/mlx5: Add structures and defines for MIRC register Saeed Mahameed
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-20 22:22 UTC (permalink / raw)
To: Saeed Mahameed, Leon Romanovsky; +Cc: netdev, linux-rdma, Eran Ben Elisha
From: Eran Ben Elisha <eranbe@mellanox.com>
On load, Driver caches MCAM (Management Capabilities Mask Register)
registers. In addition to the only MCAM register group (0) the driver
already reads, here we add support for reading groups 1 and 2.
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
drivers/net/ethernet/mellanox/mlx5/core/fw.c | 15 +++++++++------
include/linux/mlx5/device.h | 14 +++++++++++++-
include/linux/mlx5/driver.h | 2 +-
3 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index a19790dee7b2..1723229a9259 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -131,11 +131,11 @@ static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
MLX5_PCAM_REGS_5000_TO_507F);
}
-static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
+static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
+ enum mlx5_mcam_reg_groups group)
{
- return mlx5_query_mcam_reg(dev, dev->caps.mcam,
- MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
- MLX5_MCAM_REGS_FIRST_128);
+ return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
+ MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
}
static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
@@ -221,8 +221,11 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
if (MLX5_CAP_GEN(dev, pcam_reg))
mlx5_get_pcam_reg(dev);
- if (MLX5_CAP_GEN(dev, mcam_reg))
- mlx5_get_mcam_reg(dev);
+ if (MLX5_CAP_GEN(dev, mcam_reg)) {
+ mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
+ mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
+ mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
+ }
if (MLX5_CAP_GEN(dev, qcam_reg))
mlx5_get_qcam_reg(dev);
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index cc1c230f10ee..1715252b2f74 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1120,6 +1120,9 @@ enum mlx5_pcam_feature_groups {
enum mlx5_mcam_reg_groups {
MLX5_MCAM_REGS_FIRST_128 = 0x0,
+ MLX5_MCAM_REGS_0x9080_0x90FF = 0x1,
+ MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
+ MLX5_MCAM_REGS_NUM = 0x3,
};
enum mlx5_mcam_feature_groups {
@@ -1268,7 +1271,16 @@ enum mlx5_qcam_feature_groups {
MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
#define MLX5_CAP_MCAM_REG(mdev, reg) \
- MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
+ mng_access_reg_cap_mask.access_regs.reg)
+
+#define MLX5_CAP_MCAM_REG1(mdev, reg) \
+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
+ mng_access_reg_cap_mask.access_regs1.reg)
+
+#define MLX5_CAP_MCAM_REG2(mdev, reg) \
+ MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
+ mng_access_reg_cap_mask.access_regs2.reg)
#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 1884513aac90..462c67e2dc13 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -686,7 +686,7 @@ struct mlx5_core_dev {
u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
- u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
+ u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
u8 embedded_cpu;
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH mlx5-next 3/5] net/mlx5: Add structures and defines for MIRC register
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 1/5] net/mlx5: Add structures layout for new MCAM access reg groups Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 2/5] net/mlx5: Read MCAM register groups 1 and 2 Saeed Mahameed
@ 2019-11-20 22:22 ` Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 4/5] net/mlx5: Don't write read-only fields in MODIFY_HCA_VPORT_CONTEXT command Saeed Mahameed
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-20 22:22 UTC (permalink / raw)
To: Saeed Mahameed, Leon Romanovsky; +Cc: netdev, linux-rdma, Eran Ben Elisha
From: Eran Ben Elisha <eranbe@mellanox.com>
Add needed structures, layouts and defines for MIRC (Management Image
Re-activation Control) register. This structure will be used for the FSM
reactivation flow in the downstream patches.
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
include/linux/mlx5/driver.h | 1 +
include/linux/mlx5/mlx5_ifc.h | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 462c67e2dc13..d479c5e48295 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -145,6 +145,7 @@ enum {
MLX5_REG_MCC = 0x9062,
MLX5_REG_MCDA = 0x9063,
MLX5_REG_MCAM = 0x907f,
+ MLX5_REG_MIRC = 0x9162,
};
enum mlx5_qpts_trust_state {
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 97acbe8cebf8..9107c032062f 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -9456,6 +9456,13 @@ struct mlx5_ifc_mcda_reg_bits {
u8 data[0][0x20];
};
+struct mlx5_ifc_mirc_reg_bits {
+ u8 reserved_at_0[0x18];
+ u8 status_code[0x8];
+
+ u8 reserved_at_20[0x20];
+};
+
union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -9511,6 +9518,7 @@ union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
struct mlx5_ifc_mcc_reg_bits mcc_reg;
struct mlx5_ifc_mcda_reg_bits mcda_reg;
+ struct mlx5_ifc_mirc_reg_bits mirc_reg;
u8 reserved_at_0[0x60e0];
};
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH mlx5-next 4/5] net/mlx5: Don't write read-only fields in MODIFY_HCA_VPORT_CONTEXT command
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
` (2 preceding siblings ...)
2019-11-20 22:22 ` [PATCH mlx5-next 3/5] net/mlx5: Add structures and defines for MIRC register Saeed Mahameed
@ 2019-11-20 22:22 ` Saeed Mahameed
2019-11-20 22:22 ` [PATCH mlx5-next 5/5] net/mlx5: Expose resource dump register mapping Saeed Mahameed
2019-11-22 21:11 ` [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-20 22:22 UTC (permalink / raw)
To: Saeed Mahameed, Leon Romanovsky; +Cc: netdev, linux-rdma
From: Leon Romanovsky <leonro@mellanox.com>
The MODIFY_HCA_VPORT_CONTEXT uses field_selector to mask fields needed
to be written, other fields are required to be zero according to the
HW specification. The supported fields are controlled by bitfield
and limited to vport state, node and port GUIDs.
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
.../net/ethernet/mellanox/mlx5/core/vport.c | 27 +++++--------------
1 file changed, 7 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/ethernet/mellanox/mlx5/core/vport.c
index 30f7848a6f88..1faac31f74d0 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c
@@ -1064,26 +1064,13 @@ int mlx5_core_modify_hca_vport_context(struct mlx5_core_dev *dev,
ctx = MLX5_ADDR_OF(modify_hca_vport_context_in, in, hca_vport_context);
MLX5_SET(hca_vport_context, ctx, field_select, req->field_select);
- MLX5_SET(hca_vport_context, ctx, sm_virt_aware, req->sm_virt_aware);
- MLX5_SET(hca_vport_context, ctx, has_smi, req->has_smi);
- MLX5_SET(hca_vport_context, ctx, has_raw, req->has_raw);
- MLX5_SET(hca_vport_context, ctx, vport_state_policy, req->policy);
- MLX5_SET(hca_vport_context, ctx, port_physical_state, req->phys_state);
- MLX5_SET(hca_vport_context, ctx, vport_state, req->vport_state);
- MLX5_SET64(hca_vport_context, ctx, port_guid, req->port_guid);
- MLX5_SET64(hca_vport_context, ctx, node_guid, req->node_guid);
- MLX5_SET(hca_vport_context, ctx, cap_mask1, req->cap_mask1);
- MLX5_SET(hca_vport_context, ctx, cap_mask1_field_select, req->cap_mask1_perm);
- MLX5_SET(hca_vport_context, ctx, cap_mask2, req->cap_mask2);
- MLX5_SET(hca_vport_context, ctx, cap_mask2_field_select, req->cap_mask2_perm);
- MLX5_SET(hca_vport_context, ctx, lid, req->lid);
- MLX5_SET(hca_vport_context, ctx, init_type_reply, req->init_type_reply);
- MLX5_SET(hca_vport_context, ctx, lmc, req->lmc);
- MLX5_SET(hca_vport_context, ctx, subnet_timeout, req->subnet_timeout);
- MLX5_SET(hca_vport_context, ctx, sm_lid, req->sm_lid);
- MLX5_SET(hca_vport_context, ctx, sm_sl, req->sm_sl);
- MLX5_SET(hca_vport_context, ctx, qkey_violation_counter, req->qkey_violation_counter);
- MLX5_SET(hca_vport_context, ctx, pkey_violation_counter, req->pkey_violation_counter);
+ if (req->field_select & MLX5_HCA_VPORT_SEL_STATE_POLICY)
+ MLX5_SET(hca_vport_context, ctx, vport_state_policy,
+ req->policy);
+ if (req->field_select & MLX5_HCA_VPORT_SEL_PORT_GUID)
+ MLX5_SET64(hca_vport_context, ctx, port_guid, req->port_guid);
+ if (req->field_select & MLX5_HCA_VPORT_SEL_NODE_GUID)
+ MLX5_SET64(hca_vport_context, ctx, node_guid, req->node_guid);
err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
ex:
kfree(in);
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH mlx5-next 5/5] net/mlx5: Expose resource dump register mapping
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
` (3 preceding siblings ...)
2019-11-20 22:22 ` [PATCH mlx5-next 4/5] net/mlx5: Don't write read-only fields in MODIFY_HCA_VPORT_CONTEXT command Saeed Mahameed
@ 2019-11-20 22:22 ` Saeed Mahameed
2019-11-22 21:11 ` [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-20 22:22 UTC (permalink / raw)
To: Saeed Mahameed, Leon Romanovsky
Cc: netdev, linux-rdma, Aya Levin, Moshe Shemesh
From: Aya Levin <ayal@mellanox.com>
Add new register enumeration for resource dump. Add layout mapping for
resource dump: access command and response.
Signed-off-by: Aya Levin <ayal@mellanox.com>
Reviewed-by: Moshe Shemesh <moshe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
include/linux/mlx5/driver.h | 1 +
include/linux/mlx5/mlx5_ifc.h | 130 +++++++++++++++++++++++++++++++++-
2 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index d479c5e48295..8165d30e8b81 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -146,6 +146,7 @@ enum {
MLX5_REG_MCDA = 0x9063,
MLX5_REG_MCAM = 0x907f,
MLX5_REG_MIRC = 0x9162,
+ MLX5_REG_RESOURCE_DUMP = 0xC000,
};
enum mlx5_qpts_trust_state {
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 9107c032062f..a96c9ce4e27a 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -822,7 +822,9 @@ struct mlx5_ifc_qos_cap_bits {
struct mlx5_ifc_debug_cap_bits {
u8 core_dump_general[0x1];
u8 core_dump_qp[0x1];
- u8 reserved_at_2[0x1e];
+ u8 reserved_at_2[0x7];
+ u8 resource_dump[0x1];
+ u8 reserved_at_a[0x16];
u8 reserved_at_20[0x2];
u8 stall_detect[0x1];
@@ -1753,6 +1755,132 @@ struct mlx5_ifc_resize_field_select_bits {
u8 resize_field_select[0x20];
};
+struct mlx5_ifc_resource_dump_bits {
+ u8 more_dump[0x1];
+ u8 inline_dump[0x1];
+ u8 reserved_at_2[0xa];
+ u8 seq_num[0x4];
+ u8 segment_type[0x10];
+
+ u8 reserved_at_20[0x10];
+ u8 vhca_id[0x10];
+
+ u8 index1[0x20];
+
+ u8 index2[0x20];
+
+ u8 num_of_obj1[0x10];
+ u8 num_of_obj2[0x10];
+
+ u8 reserved_at_a0[0x20];
+
+ u8 device_opaque[0x40];
+
+ u8 mkey[0x20];
+
+ u8 size[0x20];
+
+ u8 address[0x40];
+
+ u8 inline_data[52][0x20];
+};
+
+struct mlx5_ifc_resource_dump_menu_record_bits {
+ u8 reserved_at_0[0x4];
+ u8 num_of_obj2_supports_active[0x1];
+ u8 num_of_obj2_supports_all[0x1];
+ u8 must_have_num_of_obj2[0x1];
+ u8 support_num_of_obj2[0x1];
+ u8 num_of_obj1_supports_active[0x1];
+ u8 num_of_obj1_supports_all[0x1];
+ u8 must_have_num_of_obj1[0x1];
+ u8 support_num_of_obj1[0x1];
+ u8 must_have_index2[0x1];
+ u8 support_index2[0x1];
+ u8 must_have_index1[0x1];
+ u8 support_index1[0x1];
+ u8 segment_type[0x10];
+
+ u8 segment_name[4][0x20];
+
+ u8 index1_name[4][0x20];
+
+ u8 index2_name[4][0x20];
+};
+
+struct mlx5_ifc_resource_dump_segment_header_bits {
+ u8 length_dw[0x10];
+ u8 segment_type[0x10];
+};
+
+struct mlx5_ifc_resource_dump_command_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+ u8 segment_called[0x10];
+ u8 vhca_id[0x10];
+
+ u8 index1[0x20];
+
+ u8 index2[0x20];
+
+ u8 num_of_obj1[0x10];
+ u8 num_of_obj2[0x10];
+};
+
+struct mlx5_ifc_resource_dump_error_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+ u8 reserved_at_20[0x10];
+ u8 syndrome_id[0x10];
+
+ u8 reserved_at_40[0x40];
+
+ u8 error[8][0x20];
+};
+
+struct mlx5_ifc_resource_dump_info_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+ u8 reserved_at_20[0x18];
+ u8 dump_version[0x8];
+
+ u8 hw_version[0x20];
+
+ u8 fw_version[0x20];
+};
+
+struct mlx5_ifc_resource_dump_menu_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+ u8 reserved_at_20[0x10];
+ u8 num_of_records[0x10];
+
+ struct mlx5_ifc_resource_dump_menu_record_bits record[0];
+};
+
+struct mlx5_ifc_resource_dump_resource_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+
+ u8 reserved_at_20[0x20];
+
+ u8 index1[0x20];
+
+ u8 index2[0x20];
+
+ u8 payload[0][0x20];
+};
+
+struct mlx5_ifc_resource_dump_terminate_segment_bits {
+ struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
+};
+
+struct mlx5_ifc_menu_resource_dump_response_bits {
+ struct mlx5_ifc_resource_dump_info_segment_bits info;
+ struct mlx5_ifc_resource_dump_command_segment_bits cmd;
+ struct mlx5_ifc_resource_dump_menu_segment_bits menu;
+ struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
+};
+
enum {
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
--
2.21.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20
2019-11-20 22:22 [PATCH mlx5-next 0/5] Mellanox, mlx5-next updates 2019-11-20 Saeed Mahameed
` (4 preceding siblings ...)
2019-11-20 22:22 ` [PATCH mlx5-next 5/5] net/mlx5: Expose resource dump register mapping Saeed Mahameed
@ 2019-11-22 21:11 ` Saeed Mahameed
5 siblings, 0 replies; 7+ messages in thread
From: Saeed Mahameed @ 2019-11-22 21:11 UTC (permalink / raw)
To: Leon Romanovsky; +Cc: netdev, linux-rdma
On Wed, 2019-11-20 at 22:22 +0000, Saeed Mahameed wrote:
> This series adds misc updates to mlx5 shared header files and, to
> include
> new HW layouts for registers that are going to be used in upcoming
> submission to net-next.
>
> From Aya, Resource dump registers for devlink health dump.
> From Eran, MCAM and MIRC registers for firmware flash re-activate
> flow.
> From Leon, Don't write read only fields to vport context.
>
> In case of no objection this series will be applied to mlx5-next tree
> and sent later as pull request to both net-next and rdma-next trees,
> with the corresponding features on top.
>
> Thanks,
> Saeed.
>
> ---
>
> Aya Levin (1):
> net/mlx5: Expose resource dump register mapping
>
> Eran Ben Elisha (3):
> net/mlx5: Add structures layout for new MCAM access reg groups
> net/mlx5: Read MCAM register groups 1 and 2
> net/mlx5: Add structures and defines for MIRC register
>
The features which need the above patches are still stuck in internal
review, i will postpone merging these patches till next kernel release.
> Leon Romanovsky (1):
> net/mlx5: Don't write read-only fields in MODIFY_HCA_VPORT_CONTEXT
> command
This one will be submitted through a pull request to net-next.
Thanks,
Saeed.
^ permalink raw reply [flat|nested] 7+ messages in thread