From: Jason Gunthorpe <jgg@ziepe.ca>
To: Liran Alon <liran.alon@oracle.com>
Cc: "Will Deacon" <will@kernel.org>,
saeedm@mellanox.com, leon@kernel.org, netdev@vger.kernel.org,
linux-rdma@vger.kernel.org, eli@mellanox.com,
tariqt@mellanox.com, danielm@mellanox.com,
"Håkon Bugge" <haakon.bugge@oracle.com>
Subject: Re: [PATCH] net: mlx5: Use writeX() to ring doorbell and remove reduntant wmb()
Date: Fri, 3 Jan 2020 12:36:06 -0400 [thread overview]
Message-ID: <20200103163606.GC9706@ziepe.ca> (raw)
In-Reply-To: <F7C45792-2F17-42AE-88A2-F744EEAD68A5@oracle.com>
On Fri, Jan 03, 2020 at 06:31:18PM +0200, Liran Alon wrote:
> > I am surprised that AMD is different here, the evolution of the WC
> > feature on x86 was to transparently speed up graphics, so I'm pretty
> > surprised AMD can get away with not ordering the same as Intel..
>
> Completely agree. I was very surprised to see this from AMD SDM and
> Optimization Guide SDM. It made sense to me too that graphics frame
> buffer is written to WC memory and then is committed to GPU by
> writing to some doorbell register mapped as UC memory.
It is possible this manual is wrong or misleading?
Having WC writes not strongly order after UC writes to the same
device, on x86, seems very, very surprising to me. Everything is
ordered on x86 :)
Jason
next prev parent reply other threads:[~2020-01-03 16:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 17:44 [PATCH] net: mlx5: Use writeX() to ring doorbell and remove reduntant wmb() Liran Alon
2020-01-02 19:29 ` Jason Gunthorpe
2020-01-02 19:45 ` Liran Alon
2020-01-02 20:58 ` Jason Gunthorpe
2020-01-02 22:21 ` Liran Alon
2020-01-03 13:37 ` Jason Gunthorpe
2020-01-03 16:31 ` Liran Alon
2020-01-03 16:36 ` Jason Gunthorpe [this message]
2020-01-03 16:42 ` Liran Alon
2020-01-03 18:38 ` Liran Alon
2020-01-03 19:06 ` Jason Gunthorpe
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