* [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09
@ 2020-08-17 12:45 Weihang Li
2020-08-17 12:45 ` [PATCH for-next 1/4] RDMA/hns: Export hardware capability flags to userspace Weihang Li
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Weihang Li @ 2020-08-17 12:45 UTC (permalink / raw)
To: dledford, jgg; +Cc: leon, linux-rdma, linuxarm
HIP09 supports larger entries/contexts to improve the performance of bus or
exchange more information with the hardware. The capbilities changes from
HIP08 to HIP09 is as follows:
- CEQE: 4B -> 64B
- AEQE: 16B -> 64B
- CQE: 32B -> 64B
- QPC: 256B -> 512B
Wenpeng Liang (3):
RDMA/hns: Add support for EQE in size of 64 Bytes
RDMA/hns: Add support for CQE in size of 64 Bytes
RDMA/hns: Add support for QPC in size of 512 Bytes
Xi Wang (1):
RDMA/hns: Export hardware capability flags to userspace
drivers/infiniband/hw/hns/hns_roce_cq.c | 19 ++++++-
drivers/infiniband/hw/hns/hns_roce_device.h | 22 ++++++--
drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 12 ++---
drivers/infiniband/hw/hns/hns_roce_hw_v1.h | 2 +-
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 79 ++++++++++++++++++++---------
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 16 ++++--
drivers/infiniband/hw/hns/hns_roce_main.c | 5 +-
include/uapi/rdma/hns-abi.h | 4 ++
8 files changed, 116 insertions(+), 43 deletions(-)
--
2.8.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH for-next 1/4] RDMA/hns: Export hardware capability flags to userspace
2020-08-17 12:45 [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09 Weihang Li
@ 2020-08-17 12:45 ` Weihang Li
2020-08-17 12:45 ` [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes Weihang Li
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Weihang Li @ 2020-08-17 12:45 UTC (permalink / raw)
To: dledford, jgg; +Cc: leon, linux-rdma, linuxarm
From: Xi Wang <wangxi11@huawei.com>
The libhns in userspace for HIP09 will use the hardware's capability to
enable some features. So export the hardware capablility flags to userspace
by reusing the reserved fields in structure
"hns_roce_ib_alloc_ucontext_resp".
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_main.c | 1 +
include/uapi/rdma/hns-abi.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index 5907cfd..98945df 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -313,6 +313,7 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
return -EAGAIN;
resp.qp_tab_size = hr_dev->caps.num_qps;
+ resp.cap_flags = (u32)hr_dev->caps.flags;
ret = hns_roce_uar_alloc(hr_dev, &context->uar);
if (ret)
diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h
index eb76b38..5c38758 100644
--- a/include/uapi/rdma/hns-abi.h
+++ b/include/uapi/rdma/hns-abi.h
@@ -73,7 +73,7 @@ struct hns_roce_ib_create_qp_resp {
struct hns_roce_ib_alloc_ucontext_resp {
__u32 qp_tab_size;
- __u32 reserved;
+ __u32 cap_flags;
};
struct hns_roce_ib_alloc_pd_resp {
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes
2020-08-17 12:45 [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09 Weihang Li
2020-08-17 12:45 ` [PATCH for-next 1/4] RDMA/hns: Export hardware capability flags to userspace Weihang Li
@ 2020-08-17 12:45 ` Weihang Li
2020-08-18 6:55 ` Lang Cheng
2020-08-17 12:45 ` [PATCH for-next 3/4] RDMA/hns: Add support for CQE " Weihang Li
2020-08-17 12:45 ` [PATCH for-next 4/4] RDMA/hns: Add support for QPC in size of 512 Bytes Weihang Li
3 siblings, 1 reply; 7+ messages in thread
From: Weihang Li @ 2020-08-17 12:45 UTC (permalink / raw)
To: dledford, jgg; +Cc: leon, linux-rdma, linuxarm
From: Wenpeng Liang <liangwenpeng@huawei.com>
The new version of RoCEE supports using CEQE in size of 4B or 64B, AEQE in
size of 16B or 64B. The performance of bus can be improved by using larger
size of EQE.
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_device.h | 13 +++++++++---
drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 10 ++++-----
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 33 ++++++++++++++++++++++-------
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 7 ++++--
4 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index 846954e..8d658a1 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -39,6 +39,7 @@
/* hip08 is a pci device */
#define PCI_REVISION_ID_HIP08 0x21
+#define PCI_REVISION_ID_HIP09 0x30
#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
@@ -78,8 +79,10 @@
#define HNS_ROCE_CEQ 0
#define HNS_ROCE_AEQ 1
-#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
-#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
+#define HNS_ROCE_CEQE_SIZE 0x4
+#define HNS_ROCE_AEQE_SIZE 0x10
+
+#define HNS_ROCE_V3_EQE_SIZE 0x40
#define HNS_ROCE_SL_SHIFT 28
#define HNS_ROCE_TCLASS_SHIFT 20
@@ -680,7 +683,8 @@ enum {
};
struct hns_roce_ceqe {
- __le32 comp;
+ __le32 comp;
+ u32 rsv[15];
};
struct hns_roce_aeqe {
@@ -717,6 +721,7 @@ struct hns_roce_aeqe {
u8 rsv0;
} __packed cmd;
} event;
+ u32 rsv[12];
};
struct hns_roce_eq {
@@ -811,6 +816,8 @@ struct hns_roce_caps {
u32 pbl_hop_num;
int aeqe_depth;
int ceqe_depth;
+ u32 aeqe_size;
+ u32 ceqe_size;
enum ib_mtu max_mtu;
u32 qpc_bt_num;
u32 qpc_timer_bt_num;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index ef7f8b3..ff76bf5 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -3775,8 +3775,7 @@ static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
{
- unsigned long off = (entry & (eq->entries - 1)) *
- HNS_ROCE_AEQ_ENTRY_SIZE;
+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
return (struct hns_roce_aeqe *)((u8 *)
(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
@@ -3881,8 +3880,7 @@ static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
{
- unsigned long off = (entry & (eq->entries - 1)) *
- HNS_ROCE_CEQ_ENTRY_SIZE;
+ unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
return (struct hns_roce_ceqe *)((u8 *)
(eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
@@ -4253,7 +4251,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
CEQ_REG_OFFSET * i;
eq->entries = hr_dev->caps.ceqe_depth;
eq->log_entries = ilog2(eq->entries);
- eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
+ eq->eqe_size = HNS_ROCE_CEQE_SIZE;
} else {
/* AEQ */
eq_table->eqc_base[i] = hr_dev->reg_base +
@@ -4263,7 +4261,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
ROCEE_CAEP_AEQE_CONS_IDX_REG;
eq->entries = hr_dev->caps.aeqe_depth;
eq->log_entries = ilog2(eq->entries);
- eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
+ eq->eqe_size = HNS_ROCE_AEQE_SIZE;
}
}
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index d51b332..882d064 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -1740,6 +1740,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
+ caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
+ caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
caps->local_ca_ack_delay = 0;
caps->max_mtu = IB_MTU_4096;
@@ -1765,6 +1767,11 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->sccc_ba_pg_sz = 0;
caps->sccc_buf_pg_sz = 0;
caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
+
+ if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
+ caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
+ caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
+ }
}
static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
@@ -1959,6 +1966,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
+ caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
+ caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
caps->mtt_ba_pg_sz = 0;
caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
@@ -1982,6 +1991,11 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
+ if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
+ caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
+ caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
+ }
+
calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
HEM_TYPE_QPC);
@@ -5223,7 +5237,7 @@ static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
aeqe = hns_roce_buf_offset(eq->mtr.kmem,
(eq->cons_index & (eq->entries - 1)) *
- HNS_ROCE_AEQ_ENTRY_SIZE);
+ eq->eqe_size);
return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
!!(eq->cons_index & eq->entries)) ? aeqe : NULL;
@@ -5323,7 +5337,8 @@ static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
ceqe = hns_roce_buf_offset(eq->mtr.kmem,
(eq->cons_index & (eq->entries - 1)) *
- HNS_ROCE_CEQ_ENTRY_SIZE);
+ eq->eqe_size);
+
return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
(!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
}
@@ -5599,14 +5614,16 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
- /* set nex_eqe_ba[43:12] */
- roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
+ roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
- /* set nex_eqe_ba[63:44] */
- roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
+ roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
+ roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
+ HNS_ROCE_EQC_EQE_SIZE_S,
+ eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
+
return 0;
}
@@ -5797,7 +5814,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
eq->type_flag = HNS_ROCE_CEQ;
eq->entries = hr_dev->caps.ceqe_depth;
- eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
+ eq->eqe_size = hr_dev->caps.ceqe_size;
eq->irq = hr_dev->irq[i + other_num + aeq_num];
eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
@@ -5806,7 +5823,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
eq->type_flag = HNS_ROCE_AEQ;
eq->entries = hr_dev->caps.aeqe_depth;
- eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
+ eq->eqe_size = hr_dev->caps.aeqe_size;
eq->irq = hr_dev->irq[i - comp_num + other_num];
eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 1fb1c58..9ed3339 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -1779,8 +1779,8 @@ struct hns_roce_eq_context {
__le32 byte_28;
__le32 byte_32;
__le32 byte_36;
- __le32 nxt_eqe_ba0;
- __le32 nxt_eqe_ba1;
+ __le32 byte_40;
+ __le32 byte_44;
__le32 rsv[5];
};
@@ -1922,6 +1922,9 @@ struct hns_roce_eq_context {
#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
+#define HNS_ROCE_EQC_EQE_SIZE_S 20
+#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
+
#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH for-next 3/4] RDMA/hns: Add support for CQE in size of 64 Bytes
2020-08-17 12:45 [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09 Weihang Li
2020-08-17 12:45 ` [PATCH for-next 1/4] RDMA/hns: Export hardware capability flags to userspace Weihang Li
2020-08-17 12:45 ` [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes Weihang Li
@ 2020-08-17 12:45 ` Weihang Li
2020-08-17 12:45 ` [PATCH for-next 4/4] RDMA/hns: Add support for QPC in size of 512 Bytes Weihang Li
3 siblings, 0 replies; 7+ messages in thread
From: Weihang Li @ 2020-08-17 12:45 UTC (permalink / raw)
To: dledford, jgg; +Cc: leon, linux-rdma, linuxarm
From: Wenpeng Liang <liangwenpeng@huawei.com>
The new version of RoCEE supports using CQE in size of 32B or 64B. The
performance of bus can be improved by using larger size of CQE.
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_cq.c | 19 ++++++++++++++++++-
drivers/infiniband/hw/hns/hns_roce_device.h | 4 ++++
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 20 +++++++++++++-------
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 5 ++++-
drivers/infiniband/hw/hns/hns_roce_main.c | 2 ++
include/uapi/rdma/hns-abi.h | 4 ++++
6 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c
index e87d616..6d237af1 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cq.c
@@ -150,7 +150,7 @@ static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
int err;
buf_attr.page_shift = hr_dev->caps.cqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
- buf_attr.region[0].size = hr_cq->cq_depth * hr_dev->caps.cq_entry_sz;
+ buf_attr.region[0].size = hr_cq->cq_depth * hr_cq->cqe_size;
buf_attr.region[0].hopnum = hr_dev->caps.cqe_hop_num;
buf_attr.region_count = 1;
buf_attr.fixed_page = true;
@@ -224,6 +224,21 @@ static void free_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
}
}
+static void set_cqe_size(struct hns_roce_cq *hr_cq, struct ib_udata *udata,
+ struct hns_roce_ib_create_cq *ucmd)
+{
+ struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
+
+ if (udata) {
+ if (udata->inlen >= offsetofend(typeof(*ucmd), cqe_size))
+ hr_cq->cqe_size = ucmd->cqe_size;
+ else
+ hr_cq->cqe_size = HNS_ROCE_V2_CQE_SIZE;
+ } else {
+ hr_cq->cqe_size = hr_dev->caps.cq_entry_sz;
+ }
+}
+
int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
struct ib_udata *udata)
{
@@ -266,6 +281,8 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
}
}
+ set_cqe_size(hr_cq, udata, &ucmd);
+
ret = alloc_cq_buf(hr_dev, hr_cq, udata, ucmd.buf_addr);
if (ret) {
ibdev_err(ibdev, "Failed to alloc CQ buf, err %d\n", ret);
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index 8d658a1..e24d88a 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -84,6 +84,9 @@
#define HNS_ROCE_V3_EQE_SIZE 0x40
+#define HNS_ROCE_V2_CQE_SIZE 32
+#define HNS_ROCE_V3_CQE_SIZE 64
+
#define HNS_ROCE_SL_SHIFT 28
#define HNS_ROCE_TCLASS_SHIFT 20
#define HNS_ROCE_FLOW_LABEL_MASK 0xfffff
@@ -472,6 +475,7 @@ struct hns_roce_cq {
void __iomem *cq_db_l;
u16 *tptr_addr;
int arm_sn;
+ int cqe_size;
unsigned long cqn;
u32 vector;
atomic_t refcount;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 882d064..e0ff87e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -1691,7 +1691,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
- caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
+ caps->cq_entry_sz = HNS_ROCE_V2_CQE_SIZE;
caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
caps->reserved_lkey = 0;
caps->reserved_pds = 0;
@@ -1771,6 +1771,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
+ caps->cq_entry_sz = HNS_ROCE_V3_CQE_SIZE;
}
}
@@ -1863,7 +1864,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
- caps->cq_entry_sz = resp_a->cq_entry_sz;
+ caps->cq_entry_sz = HNS_ROCE_V2_CQE_SIZE;
caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
caps->irrl_entry_sz = resp_b->irrl_entry_sz;
@@ -1994,6 +1995,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
+ caps->cq_entry_sz = HNS_ROCE_V3_CQE_SIZE;
}
calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
@@ -2771,8 +2773,7 @@ static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
{
- return hns_roce_buf_offset(hr_cq->mtr.kmem,
- n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
+ return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
}
static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
@@ -2872,6 +2873,10 @@ static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
+ roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQE_SIZE_M,
+ V2_CQC_BYTE_8_CQE_SIZE_S, hr_cq->cqe_size ==
+ HNS_ROCE_V3_CQE_SIZE ? 1 : 0);
+
cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
roce_set_field(cq_context->byte_16_hop_addr,
@@ -3039,7 +3044,8 @@ static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
}
static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
- struct hns_roce_v2_cqe *cqe, struct ib_wc *wc)
+ struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
+ struct ib_wc *wc)
{
static const struct {
u32 cqe_status;
@@ -3080,7 +3086,7 @@ static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
- sizeof(*cqe), false);
+ cq->cqe_size, false);
/*
* For hns ROCEE, GENERAL_ERR is an error type that is not defined in
@@ -3177,7 +3183,7 @@ static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
++wq->tail;
}
- get_cqe_status(hr_dev, *cur_qp, cqe, wc);
+ get_cqe_status(hr_dev, *cur_qp, hr_cq, cqe, wc);
if (unlikely(wc->status != IB_WC_SUCCESS))
return 0;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 9ed3339..059e308 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -86,7 +86,6 @@
#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
#define HNS_ROCE_V2_IDX_ENTRY_SZ 4
-#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
#define HNS_ROCE_V2_SCCC_ENTRY_SZ 32
#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
@@ -311,6 +310,9 @@ struct hns_roce_v2_cq_context {
#define V2_CQC_BYTE_8_CQN_S 0
#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
+#define V2_CQC_BYTE_8_CQE_SIZE_S 27
+#define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
+
#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
@@ -898,6 +900,7 @@ struct hns_roce_v2_cqe {
u8 smac[4];
__le32 byte_28;
__le32 byte_32;
+ __le32 rsv[8];
};
#define V2_CQE_BYTE_4_OPCODE_S 0
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index 98945df..2213c75 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -324,6 +324,8 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
mutex_init(&context->page_mutex);
}
+ resp.cqe_size = hr_dev->caps.cq_entry_sz;
+
ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
if (ret)
goto error_fail_copy_to_udata;
diff --git a/include/uapi/rdma/hns-abi.h b/include/uapi/rdma/hns-abi.h
index 5c38758..99a11b6 100644
--- a/include/uapi/rdma/hns-abi.h
+++ b/include/uapi/rdma/hns-abi.h
@@ -39,6 +39,8 @@
struct hns_roce_ib_create_cq {
__aligned_u64 buf_addr;
__aligned_u64 db_addr;
+ __u32 cqe_size;
+ __u32 reserved;
};
struct hns_roce_ib_create_cq_resp {
@@ -74,6 +76,8 @@ struct hns_roce_ib_create_qp_resp {
struct hns_roce_ib_alloc_ucontext_resp {
__u32 qp_tab_size;
__u32 cap_flags;
+ __u32 cqe_size;
+ __u32 reserved;
};
struct hns_roce_ib_alloc_pd_resp {
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH for-next 4/4] RDMA/hns: Add support for QPC in size of 512 Bytes
2020-08-17 12:45 [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09 Weihang Li
` (2 preceding siblings ...)
2020-08-17 12:45 ` [PATCH for-next 3/4] RDMA/hns: Add support for CQE " Weihang Li
@ 2020-08-17 12:45 ` Weihang Li
3 siblings, 0 replies; 7+ messages in thread
From: Weihang Li @ 2020-08-17 12:45 UTC (permalink / raw)
To: dledford, jgg; +Cc: leon, linux-rdma, linuxarm
From: Wenpeng Liang <liangwenpeng@huawei.com>
The new version of RoCEE supports using QPC in size of 256B or 512B, so
that HIP09 can supports new congestion control algorithms by using QPC in
larger size.
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_device.h | 5 ++++-
drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 2 +-
drivers/infiniband/hw/hns/hns_roce_hw_v1.h | 2 +-
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 26 +++++++++++++++++---------
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 4 ++--
drivers/infiniband/hw/hns/hns_roce_main.c | 2 +-
6 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index e24d88a..876bcd2 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -87,6 +87,9 @@
#define HNS_ROCE_V2_CQE_SIZE 32
#define HNS_ROCE_V3_CQE_SIZE 64
+#define HNS_ROCE_V2_QPC_SZ 256
+#define HNS_ROCE_V3_QPC_SZ 512
+
#define HNS_ROCE_SL_SHIFT 28
#define HNS_ROCE_TCLASS_SHIFT 20
#define HNS_ROCE_FLOW_LABEL_MASK 0xfffff
@@ -806,7 +809,7 @@ struct hns_roce_caps {
u32 page_size_cap;
u32 reserved_lkey;
int mtpt_entry_sz;
- int qpc_entry_sz;
+ int qpc_sz;
int irrl_entry_sz;
int trrl_entry_sz;
int cqc_entry_sz;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index ff76bf5..4aaca5e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -1471,7 +1471,7 @@ static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
- caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
+ caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
index 52307b2..b0404d9 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
@@ -68,7 +68,7 @@
#define HNS_ROCE_V1_COMP_EQE_NUM 0x8000
#define HNS_ROCE_V1_ASYNC_EQE_NUM 0x400
-#define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
+#define HNS_ROCE_V1_QPC_SIZE 256
#define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
#define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
#define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index e0ff87e..76e0a1d 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -1683,7 +1683,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
- caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
+ caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
@@ -1772,6 +1772,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->cq_entry_sz = HNS_ROCE_V3_CQE_SIZE;
+ caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
}
}
@@ -1874,7 +1875,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
caps->idx_entry_sz = resp_b->idx_entry_sz;
caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz;
caps->max_mtu = resp_b->max_mtu;
- caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz);
+ caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
caps->min_cqes = resp_b->min_cqes;
caps->min_wqes = resp_b->min_wqes;
caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
@@ -1996,9 +1997,10 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
caps->cq_entry_sz = HNS_ROCE_V3_CQE_SIZE;
+ caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
}
- calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
+ calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
HEM_TYPE_QPC);
calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
@@ -3534,16 +3536,21 @@ static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
struct hns_roce_v2_qp_context *context,
+ struct hns_roce_v2_qp_context *qpc_mask,
struct hns_roce_qp *hr_qp)
{
struct hns_roce_cmd_mailbox *mailbox;
+ int qpc_size;
int ret;
mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
if (IS_ERR(mailbox))
return PTR_ERR(mailbox);
- memcpy(mailbox->buf, context, sizeof(*context) * 2);
+ /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
+ qpc_size = hr_dev->caps.qpc_sz;
+ memcpy(mailbox->buf, context, qpc_size);
+ memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
HNS_ROCE_CMD_MODIFY_QPC,
@@ -4319,7 +4326,7 @@ static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
}
if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
- memset(qpc_mask, 0, sizeof(*qpc_mask));
+ memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
qpc_mask);
} else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
@@ -4542,8 +4549,9 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
* we should set all bits of the relevant fields in context mask to
* 0 at the same time, else set them to 0x1.
*/
- memset(context, 0, sizeof(*context));
- memset(qpc_mask, 0xff, sizeof(*qpc_mask));
+ memset(context, 0, hr_dev->caps.qpc_sz);
+ memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
+
ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
new_state, context, qpc_mask);
if (ret)
@@ -4593,7 +4601,7 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
V2_QPC_BYTE_60_QP_ST_S, 0);
/* SW pass context to HW */
- ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp);
+ ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
if (ret) {
ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret);
goto out;
@@ -4656,7 +4664,7 @@ static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
if (ret)
goto out;
- memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
+ memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz);
out:
hns_roce_free_cmd_mailbox(hr_dev, mailbox);
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 059e308..07a74df 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -77,7 +77,6 @@
#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
-#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
#define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100
@@ -516,6 +515,7 @@ struct hns_roce_v2_qp_context {
__le32 byte_248_ack_psn;
__le32 byte_252_err_txcqn;
__le32 byte_256_sqflush_rqcqe;
+ __le32 ext[64];
};
#define V2_QPC_BYTE_4_TST_S 0
@@ -1588,7 +1588,7 @@ struct hns_roce_query_pf_caps_b {
u8 idx_entry_sz;
u8 scc_ctx_entry_sz;
u8 max_mtu;
- __le16 qpc_entry_sz;
+ __le16 qpc_sz;
__le16 qpc_timer_entry_sz;
__le16 cqc_timer_entry_sz;
u8 min_cqes;
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index 2213c75..015186a 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -590,7 +590,7 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
}
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
- HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
+ HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
hr_dev->caps.num_qps, 1);
if (ret) {
dev_err(dev, "Failed to init QP context memory, aborting.\n");
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes
2020-08-17 12:45 ` [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes Weihang Li
@ 2020-08-18 6:55 ` Lang Cheng
2020-08-19 1:18 ` liweihang
0 siblings, 1 reply; 7+ messages in thread
From: Lang Cheng @ 2020-08-18 6:55 UTC (permalink / raw)
To: Weihang Li, dledford, jgg; +Cc: leon, linux-rdma, linuxarm
On 2020/8/17 20:45, Weihang Li wrote:
> From: Wenpeng Liang <liangwenpeng@huawei.com>
>
> The new version of RoCEE supports using CEQE in size of 4B or 64B, AEQE in
> size of 16B or 64B. The performance of bus can be improved by using larger
> size of EQE.
>
> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
> Signed-off-by: Weihang Li <liweihang@huawei.com>
> ---
> drivers/infiniband/hw/hns/hns_roce_device.h | 13 +++++++++---
> drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 10 ++++-----
> drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 33 ++++++++++++++++++++++-------
> drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 7 ++++--
> 4 files changed, 44 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
> index 846954e..8d658a1 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_device.h
> +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
> @@ -39,6 +39,7 @@
>
> /* hip08 is a pci device */
May delete this comment?
> #define PCI_REVISION_ID_HIP08 0x21
> +#define PCI_REVISION_ID_HIP09 0x30
>
> #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
>
> @@ -78,8 +79,10 @@
> #define HNS_ROCE_CEQ 0
> #define HNS_ROCE_AEQ 1
>
> -#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
> -#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
> +#define HNS_ROCE_CEQE_SIZE 0x4
> +#define HNS_ROCE_AEQE_SIZE 0x10
> +
> +#define HNS_ROCE_V3_EQE_SIZE 0x40
>
> #define HNS_ROCE_SL_SHIFT 28
> #define HNS_ROCE_TCLASS_SHIFT 20
> @@ -680,7 +683,8 @@ enum {
> };
>
> struct hns_roce_ceqe {
> - __le32 comp;
> + __le32 comp;
> + u32 rsv[15];
__le32.
> };
>
> struct hns_roce_aeqe {
> @@ -717,6 +721,7 @@ struct hns_roce_aeqe {
> u8 rsv0;
> } __packed cmd;
> } event;
> + u32 rsv[12];
ditto. Seems they are not new issues.
> };
>
> struct hns_roce_eq {
> @@ -811,6 +816,8 @@ struct hns_roce_caps {
> u32 pbl_hop_num;
> int aeqe_depth;
> int ceqe_depth;
> + u32 aeqe_size;
> + u32 ceqe_size;
> enum ib_mtu max_mtu;
> u32 qpc_bt_num;
> u32 qpc_timer_bt_num;
> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
> index ef7f8b3..ff76bf5 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
> @@ -3775,8 +3775,7 @@ static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
>
> static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
> {
> - unsigned long off = (entry & (eq->entries - 1)) *
> - HNS_ROCE_AEQ_ENTRY_SIZE;
> + unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
>
> return (struct hns_roce_aeqe *)((u8 *)
> (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
> @@ -3881,8 +3880,7 @@ static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
>
> static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
> {
> - unsigned long off = (entry & (eq->entries - 1)) *
> - HNS_ROCE_CEQ_ENTRY_SIZE;
> + unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
>
> return (struct hns_roce_ceqe *)((u8 *)
> (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
> @@ -4253,7 +4251,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
> CEQ_REG_OFFSET * i;
> eq->entries = hr_dev->caps.ceqe_depth;
> eq->log_entries = ilog2(eq->entries);
> - eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
> + eq->eqe_size = HNS_ROCE_CEQE_SIZE;
> } else {
> /* AEQ */
> eq_table->eqc_base[i] = hr_dev->reg_base +
> @@ -4263,7 +4261,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
> ROCEE_CAEP_AEQE_CONS_IDX_REG;
> eq->entries = hr_dev->caps.aeqe_depth;
> eq->log_entries = ilog2(eq->entries);
> - eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
> + eq->eqe_size = HNS_ROCE_AEQE_SIZE;
> }
> }
>
> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> index d51b332..882d064 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
> @@ -1740,6 +1740,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
> caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
> caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
> caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
> + caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
> + caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
> caps->local_ca_ack_delay = 0;
> caps->max_mtu = IB_MTU_4096;
>
> @@ -1765,6 +1767,11 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
> caps->sccc_ba_pg_sz = 0;
> caps->sccc_buf_pg_sz = 0;
> caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
> +
> + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
> + caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
> + caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
> + }
> }
>
> static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
> @@ -1959,6 +1966,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
> caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
> caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
> caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
> + caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
> + caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
> caps->mtt_ba_pg_sz = 0;
> caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
> caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
> @@ -1982,6 +1991,11 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
> V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
> V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
>
> + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
> + caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
> + caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
> + }
> +
> calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
> caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
> HEM_TYPE_QPC);
> @@ -5223,7 +5237,7 @@ static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
>
> aeqe = hns_roce_buf_offset(eq->mtr.kmem,
> (eq->cons_index & (eq->entries - 1)) *
> - HNS_ROCE_AEQ_ENTRY_SIZE);
> + eq->eqe_size);
>
> return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
> !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
> @@ -5323,7 +5337,8 @@ static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
>
> ceqe = hns_roce_buf_offset(eq->mtr.kmem,
> (eq->cons_index & (eq->entries - 1)) *
> - HNS_ROCE_CEQ_ENTRY_SIZE);
> + eq->eqe_size);
> +
> return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
> (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
> }
> @@ -5599,14 +5614,16 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
> roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
> HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
>
> - /* set nex_eqe_ba[43:12] */
> - roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
> + roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
> HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
>
> - /* set nex_eqe_ba[63:44] */
> - roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
> + roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
> HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
>
> + roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
> + HNS_ROCE_EQC_EQE_SIZE_S,
> + eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
> +
> return 0;
> }
>
> @@ -5797,7 +5814,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
> eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
> eq->type_flag = HNS_ROCE_CEQ;
> eq->entries = hr_dev->caps.ceqe_depth;
> - eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
> + eq->eqe_size = hr_dev->caps.ceqe_size;
> eq->irq = hr_dev->irq[i + other_num + aeq_num];
> eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
> eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
> @@ -5806,7 +5823,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
> eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
> eq->type_flag = HNS_ROCE_AEQ;
> eq->entries = hr_dev->caps.aeqe_depth;
> - eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
> + eq->eqe_size = hr_dev->caps.aeqe_size;
> eq->irq = hr_dev->irq[i - comp_num + other_num];
> eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
> eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
> index 1fb1c58..9ed3339 100644
> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
> @@ -1779,8 +1779,8 @@ struct hns_roce_eq_context {
> __le32 byte_28;
> __le32 byte_32;
> __le32 byte_36;
> - __le32 nxt_eqe_ba0;
> - __le32 nxt_eqe_ba1;
> + __le32 byte_40;
> + __le32 byte_44;
> __le32 rsv[5];
> };
>
> @@ -1922,6 +1922,9 @@ struct hns_roce_eq_context {
> #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
> #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
>
> +#define HNS_ROCE_EQC_EQE_SIZE_S 20
> +#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
> +
> #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
> #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes
2020-08-18 6:55 ` Lang Cheng
@ 2020-08-19 1:18 ` liweihang
0 siblings, 0 replies; 7+ messages in thread
From: liweihang @ 2020-08-19 1:18 UTC (permalink / raw)
To: chenglang, dledford, jgg; +Cc: leon, linux-rdma, Linuxarm
On 2020/8/18 14:55, chenglang wrote:
>
>
> On 2020/8/17 20:45, Weihang Li wrote:
>> From: Wenpeng Liang <liangwenpeng@huawei.com>
>>
>> The new version of RoCEE supports using CEQE in size of 4B or 64B, AEQE in
>> size of 16B or 64B. The performance of bus can be improved by using larger
>> size of EQE.
>>
>> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
>> Signed-off-by: Weihang Li <liweihang@huawei.com>
>> ---
>> drivers/infiniband/hw/hns/hns_roce_device.h | 13 +++++++++---
>> drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 10 ++++-----
>> drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 33 ++++++++++++++++++++++-------
>> drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 7 ++++--
>> 4 files changed, 44 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
>> index 846954e..8d658a1 100644
>> --- a/drivers/infiniband/hw/hns/hns_roce_device.h
>> +++ b/drivers/infiniband/hw/hns/hns_roce_device.h
>> @@ -39,6 +39,7 @@
>>
>> /* hip08 is a pci device */
>
> May delete this comment?
OK, will remove it, thank you.
>
>> #define PCI_REVISION_ID_HIP08 0x21
>> +#define PCI_REVISION_ID_HIP09 0x30
>>
>> #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
>>
>> @@ -78,8 +79,10 @@
>> #define HNS_ROCE_CEQ 0
>> #define HNS_ROCE_AEQ 1
>>
>> -#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
>> -#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
>> +#define HNS_ROCE_CEQE_SIZE 0x4
>> +#define HNS_ROCE_AEQE_SIZE 0x10
>> +
>> +#define HNS_ROCE_V3_EQE_SIZE 0x40
>>
>> #define HNS_ROCE_SL_SHIFT 28
>> #define HNS_ROCE_TCLASS_SHIFT 20
>> @@ -680,7 +683,8 @@ enum {
>> };
>>
>> struct hns_roce_ceqe {
>> - __le32 comp;
>> + __le32 comp;
>> + u32 rsv[15];
>
>
> __le32.
OK.
>
>
>> };
>>
>> struct hns_roce_aeqe {
>> @@ -717,6 +721,7 @@ struct hns_roce_aeqe {
>> u8 rsv0;
>> } __packed cmd;
>> } event;
>> + u32 rsv[12];
>
>
> ditto. Seems they are not new issues.
>
OK.
Thanks,
Weihang
>
>> };
>>
>> struct hns_roce_eq {
>> @@ -811,6 +816,8 @@ struct hns_roce_caps {
>> u32 pbl_hop_num;
>> int aeqe_depth;
>> int ceqe_depth;
>> + u32 aeqe_size;
>> + u32 ceqe_size;
>> enum ib_mtu max_mtu;
>> u32 qpc_bt_num;
>> u32 qpc_timer_bt_num;
>> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
>> index ef7f8b3..ff76bf5 100644
>> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
>> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
>> @@ -3775,8 +3775,7 @@ static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
>>
>> static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
>> {
>> - unsigned long off = (entry & (eq->entries - 1)) *
>> - HNS_ROCE_AEQ_ENTRY_SIZE;
>> + unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
>>
>> return (struct hns_roce_aeqe *)((u8 *)
>> (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
>> @@ -3881,8 +3880,7 @@ static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
>>
>> static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
>> {
>> - unsigned long off = (entry & (eq->entries - 1)) *
>> - HNS_ROCE_CEQ_ENTRY_SIZE;
>> + unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
>>
>> return (struct hns_roce_ceqe *)((u8 *)
>> (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
>> @@ -4253,7 +4251,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
>> CEQ_REG_OFFSET * i;
>> eq->entries = hr_dev->caps.ceqe_depth;
>> eq->log_entries = ilog2(eq->entries);
>> - eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
>> + eq->eqe_size = HNS_ROCE_CEQE_SIZE;
>> } else {
>> /* AEQ */
>> eq_table->eqc_base[i] = hr_dev->reg_base +
>> @@ -4263,7 +4261,7 @@ static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
>> ROCEE_CAEP_AEQE_CONS_IDX_REG;
>> eq->entries = hr_dev->caps.aeqe_depth;
>> eq->log_entries = ilog2(eq->entries);
>> - eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
>> + eq->eqe_size = HNS_ROCE_AEQE_SIZE;
>> }
>> }
>>
>> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
>> index d51b332..882d064 100644
>> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
>> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
>> @@ -1740,6 +1740,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
>> caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
>> caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
>> caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
>> + caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
>> + caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
>> caps->local_ca_ack_delay = 0;
>> caps->max_mtu = IB_MTU_4096;
>>
>> @@ -1765,6 +1767,11 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
>> caps->sccc_ba_pg_sz = 0;
>> caps->sccc_buf_pg_sz = 0;
>> caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
>> +
>> + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
>> + caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
>> + caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
>> + }
>> }
>>
>> static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
>> @@ -1959,6 +1966,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
>> caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
>> caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
>> caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
>> + caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
>> + caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
>> caps->mtt_ba_pg_sz = 0;
>> caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
>> caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
>> @@ -1982,6 +1991,11 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
>> V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
>> V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
>>
>> + if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
>> + caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
>> + caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
>> + }
>> +
>> calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
>> caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
>> HEM_TYPE_QPC);
>> @@ -5223,7 +5237,7 @@ static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
>>
>> aeqe = hns_roce_buf_offset(eq->mtr.kmem,
>> (eq->cons_index & (eq->entries - 1)) *
>> - HNS_ROCE_AEQ_ENTRY_SIZE);
>> + eq->eqe_size);
>>
>> return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
>> !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
>> @@ -5323,7 +5337,8 @@ static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
>>
>> ceqe = hns_roce_buf_offset(eq->mtr.kmem,
>> (eq->cons_index & (eq->entries - 1)) *
>> - HNS_ROCE_CEQ_ENTRY_SIZE);
>> + eq->eqe_size);
>> +
>> return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
>> (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
>> }
>> @@ -5599,14 +5614,16 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
>> roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
>> HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
>>
>> - /* set nex_eqe_ba[43:12] */
>> - roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
>> + roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
>> HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
>>
>> - /* set nex_eqe_ba[63:44] */
>> - roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
>> + roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
>> HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
>>
>> + roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
>> + HNS_ROCE_EQC_EQE_SIZE_S,
>> + eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
>> +
>> return 0;
>> }
>>
>> @@ -5797,7 +5814,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
>> eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
>> eq->type_flag = HNS_ROCE_CEQ;
>> eq->entries = hr_dev->caps.ceqe_depth;
>> - eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
>> + eq->eqe_size = hr_dev->caps.ceqe_size;
>> eq->irq = hr_dev->irq[i + other_num + aeq_num];
>> eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
>> eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
>> @@ -5806,7 +5823,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
>> eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
>> eq->type_flag = HNS_ROCE_AEQ;
>> eq->entries = hr_dev->caps.aeqe_depth;
>> - eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
>> + eq->eqe_size = hr_dev->caps.aeqe_size;
>> eq->irq = hr_dev->irq[i - comp_num + other_num];
>> eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
>> eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
>> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
>> index 1fb1c58..9ed3339 100644
>> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
>> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
>> @@ -1779,8 +1779,8 @@ struct hns_roce_eq_context {
>> __le32 byte_28;
>> __le32 byte_32;
>> __le32 byte_36;
>> - __le32 nxt_eqe_ba0;
>> - __le32 nxt_eqe_ba1;
>> + __le32 byte_40;
>> + __le32 byte_44;
>> __le32 rsv[5];
>> };
>>
>> @@ -1922,6 +1922,9 @@ struct hns_roce_eq_context {
>> #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
>> #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
>>
>> +#define HNS_ROCE_EQC_EQE_SIZE_S 20
>> +#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
>> +
>> #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
>> #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
>>
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-08-19 1:18 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-17 12:45 [PATCH for-next 0/4] RDMA/hns: Extend some capabilities for HIP09 Weihang Li
2020-08-17 12:45 ` [PATCH for-next 1/4] RDMA/hns: Export hardware capability flags to userspace Weihang Li
2020-08-17 12:45 ` [PATCH for-next 2/4] RDMA/hns: Add support for EQE in size of 64 Bytes Weihang Li
2020-08-18 6:55 ` Lang Cheng
2020-08-19 1:18 ` liweihang
2020-08-17 12:45 ` [PATCH for-next 3/4] RDMA/hns: Add support for CQE " Weihang Li
2020-08-17 12:45 ` [PATCH for-next 4/4] RDMA/hns: Add support for QPC in size of 512 Bytes Weihang Li
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