* [PATCH 0/2] Drop all accesses to MPSS PERPH register space
@ 2020-04-15 14:51 Sibi Sankar
2020-04-15 14:51 ` [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs Sibi Sankar
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Sibi Sankar @ 2020-04-15 14:51 UTC (permalink / raw)
To: bjorn.andersson, robh+dt
Cc: agross, linux-arm-msm, linux-remoteproc, linux-kernel, evgreen,
ohad, Sibi Sankar
7C retail devices using MSA based boot will result in a fuse combination
which will prevent accesses to MSS PERPH register space where the mpss
clocks and halt-nav reside. Hence requesting a halt-nav as part of the
SSR sequence will result in a NoC error. Issuing HALT NAV request and
turning on the mss clocks as part of SSR will no longer be required
since the modem firmware will have the necessary fixes to ensure that
there are no pending NAV DMA transactions thereby ensuring a smooth
SSR.
Sibi Sankar (2):
dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs
remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space
.../bindings/remoteproc/qcom,q6v5.txt | 14 +--
drivers/remoteproc/qcom_q6v5_mss.c | 102 ++++--------------
2 files changed, 23 insertions(+), 93 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs 2020-04-15 14:51 [PATCH 0/2] Drop all accesses to MPSS PERPH register space Sibi Sankar @ 2020-04-15 14:51 ` Sibi Sankar 2020-04-15 14:51 ` Sibi Sankar 2020-04-15 14:51 ` [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space Sibi Sankar ` (2 subsequent siblings) 3 siblings, 1 reply; 7+ messages in thread From: Sibi Sankar @ 2020-04-15 14:51 UTC (permalink / raw) To: bjorn.andersson, robh+dt Cc: agross, linux-arm-msm, linux-remoteproc, linux-kernel, evgreen, ohad, Sibi Sankar 7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. However accesses to conn_box_spare0 in TCSR register space is still permitted so rename the binding appropriately to qcom,spare-regs and drop all accesses to the MPSS PERPH register space. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 88dfa3fc15f78..607957ad32e7b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -79,7 +79,7 @@ on the Qualcomm Hexagon core. "snoc_axi", "mnoc_axi", "qdss" qcom,sc7180-mss-pil: must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi", - "mss_crypto", "mss_nav", "nav" + "nav" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" @@ -173,16 +173,12 @@ For the compatible string below the following supplies are required: For the compatible strings below the following phandle references are required: "qcom,sc7180-mss-pil" -- qcom,halt-nav-regs: +- qcom,spare-regs: Usage: required Value type: <prop-encoded-array> - Definition: reference to a list of 2 phandles with one offset each for - the modem sub-system running on SC7180 SoC. The first - phandle reference is to the mss clock node followed by the - offset within register space for nav halt register. The - second phandle reference is to a syscon representing TCSR - followed by the offset within syscon for conn_box_spare0 - register. + Definition: a phandle reference to a syscon representing TCSR followed + by the offset within syscon for conn_box_spare0 register + used by the modem sub-system running on SC7180 SoC. = SUBNODES: The Hexagon node must contain two subnodes, named "mba" and "mpss" representing -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs 2020-04-15 14:51 ` [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs Sibi Sankar @ 2020-04-15 14:51 ` Sibi Sankar 0 siblings, 0 replies; 7+ messages in thread From: Sibi Sankar @ 2020-04-15 14:51 UTC (permalink / raw) To: bjorn.andersson, robh+dt Cc: agross, linux-arm-msm, linux-remoteproc, linux-kernel, evgreen, ohad, Sibi Sankar 7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. However accesses to conn_box_spare0 in TCSR register space is still permitted so rename the binding appropriately to qcom,spare-regs and drop all accesses to the MPSS PERPH register space. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 88dfa3fc15f78..607957ad32e7b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -79,7 +79,7 @@ on the Qualcomm Hexagon core. "snoc_axi", "mnoc_axi", "qdss" qcom,sc7180-mss-pil: must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi", - "mss_crypto", "mss_nav", "nav" + "nav" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" @@ -173,16 +173,12 @@ For the compatible string below the following supplies are required: For the compatible strings below the following phandle references are required: "qcom,sc7180-mss-pil" -- qcom,halt-nav-regs: +- qcom,spare-regs: Usage: required Value type: <prop-encoded-array> - Definition: reference to a list of 2 phandles with one offset each for - the modem sub-system running on SC7180 SoC. The first - phandle reference is to the mss clock node followed by the - offset within register space for nav halt register. The - second phandle reference is to a syscon representing TCSR - followed by the offset within syscon for conn_box_spare0 - register. + Definition: a phandle reference to a syscon representing TCSR followed + by the offset within syscon for conn_box_spare0 register + used by the modem sub-system running on SC7180 SoC. = SUBNODES: The Hexagon node must contain two subnodes, named "mba" and "mpss" representing -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space 2020-04-15 14:51 [PATCH 0/2] Drop all accesses to MPSS PERPH register space Sibi Sankar 2020-04-15 14:51 ` [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs Sibi Sankar @ 2020-04-15 14:51 ` Sibi Sankar 2020-04-15 14:51 ` Sibi Sankar 2020-04-29 17:27 ` [PATCH 0/2] Drop all " Evan Green 2020-05-13 6:20 ` patchwork-bot+linux-remoteproc 3 siblings, 1 reply; 7+ messages in thread From: Sibi Sankar @ 2020-04-15 14:51 UTC (permalink / raw) To: bjorn.andersson, robh+dt Cc: agross, linux-arm-msm, linux-remoteproc, linux-kernel, evgreen, ohad, Sibi Sankar 7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. So drop all accesses to the MPSS PERPH register space. Issuing HALT NAV request and turning on the mss clocks as part of SSR will no longer be required since the modem firmware will have the necessary fixes to ensure that there are no pending NAV DMA transactions. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_mss.c | 102 +++++------------------------ 1 file changed, 18 insertions(+), 84 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 6a19e0e77236e..3a7352776a319 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -69,13 +69,9 @@ #define AXI_HALTREQ_REG 0x0 #define AXI_HALTACK_REG 0x4 #define AXI_IDLE_REG 0x8 -#define NAV_AXI_HALTREQ_BIT BIT(0) -#define NAV_AXI_HALTACK_BIT BIT(1) -#define NAV_AXI_IDLE_BIT BIT(2) #define AXI_GATING_VALID_OVERRIDE BIT(0) #define HALT_ACK_TIMEOUT_US 100000 -#define NAV_HALT_ACK_TIMEOUT_US 200 /* QDSP6SS_RESET */ #define Q6SS_STOP_CORE BIT(0) @@ -143,7 +139,7 @@ struct rproc_hexagon_res { int version; bool need_mem_protection; bool has_alt_reset; - bool has_halt_nav; + bool has_spare_reg; }; struct q6v5 { @@ -154,13 +150,11 @@ struct q6v5 { void __iomem *rmb_base; struct regmap *halt_map; - struct regmap *halt_nav_map; struct regmap *conn_map; u32 halt_q6; u32 halt_modem; u32 halt_nc; - u32 halt_nav; u32 conn_box; struct reset_control *mss_restart; @@ -205,7 +199,7 @@ struct q6v5 { struct qcom_sysmon *sysmon; bool need_mem_protection; bool has_alt_reset; - bool has_halt_nav; + bool has_spare_reg; int mpss_perm; int mba_perm; const char *hexagon_mdt_image; @@ -426,21 +420,19 @@ static int q6v5_reset_assert(struct q6v5 *qproc) reset_control_assert(qproc->pdc_reset); ret = reset_control_reset(qproc->mss_restart); reset_control_deassert(qproc->pdc_reset); - } else if (qproc->has_halt_nav) { + } else if (qproc->has_spare_reg) { /* * When the AXI pipeline is being reset with the Q6 modem partly * operational there is possibility of AXI valid signal to * glitch, leading to spurious transactions and Q6 hangs. A work * around is employed by asserting the AXI_GATING_VALID_OVERRIDE - * BIT before triggering Q6 MSS reset. Both the HALTREQ and - * AXI_GATING_VALID_OVERRIDE are withdrawn post MSS assert - * followed by a MSS deassert, while holding the PDC reset. + * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE + * is withdrawn post MSS assert followed by a MSS deassert, + * while holding the PDC reset. */ reset_control_assert(qproc->pdc_reset); regmap_update_bits(qproc->conn_map, qproc->conn_box, AXI_GATING_VALID_OVERRIDE, 1); - regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav, - NAV_AXI_HALTREQ_BIT, 0); reset_control_assert(qproc->mss_restart); reset_control_deassert(qproc->pdc_reset); regmap_update_bits(qproc->conn_map, qproc->conn_box, @@ -463,7 +455,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc) ret = reset_control_reset(qproc->mss_restart); writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); reset_control_deassert(qproc->pdc_reset); - } else if (qproc->has_halt_nav) { + } else if (qproc->has_spare_reg) { ret = reset_control_reset(qproc->mss_restart); } else { ret = reset_control_deassert(qproc->mss_restart); @@ -760,32 +752,6 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc, regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); } -static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc, - struct regmap *halt_map, - u32 offset) -{ - unsigned int val; - int ret; - - /* Check if we're already idle */ - ret = regmap_read(halt_map, offset, &val); - if (!ret && (val & NAV_AXI_IDLE_BIT)) - return; - - /* Assert halt request */ - regmap_update_bits(halt_map, offset, NAV_AXI_HALTREQ_BIT, - NAV_AXI_HALTREQ_BIT); - - /* Wait for halt ack*/ - regmap_read_poll_timeout(halt_map, offset, val, - (val & NAV_AXI_HALTACK_BIT), - 5, NAV_HALT_ACK_TIMEOUT_US); - - ret = regmap_read(halt_map, offset, &val); - if (ret || !(val & NAV_AXI_IDLE_BIT)) - dev_err(qproc->dev, "port failed halt\n"); -} - static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) { unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; @@ -950,9 +916,6 @@ static int q6v5_mba_load(struct q6v5 *qproc) halt_axi_ports: q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); - if (qproc->has_halt_nav) - q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, - qproc->halt_nav); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); reclaim_mba: @@ -1000,9 +963,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); - if (qproc->has_halt_nav) - q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, - qproc->halt_nav); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); if (qproc->version == MSS_MSM8996) { /* @@ -1433,36 +1393,12 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) qproc->halt_modem = args.args[1]; qproc->halt_nc = args.args[2]; - if (qproc->has_halt_nav) { - struct platform_device *nav_pdev; - + if (qproc->has_spare_reg) { ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-nav-regs", + "qcom,spare-regs", 1, 0, &args); if (ret < 0) { - dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); - return -EINVAL; - } - - nav_pdev = of_find_device_by_node(args.np); - of_node_put(args.np); - if (!nav_pdev) { - dev_err(&pdev->dev, "failed to get mss clock device\n"); - return -EPROBE_DEFER; - } - - qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, NULL); - if (!qproc->halt_nav_map) { - dev_err(&pdev->dev, "failed to get map from device\n"); - return -EINVAL; - } - qproc->halt_nav = args.args[0]; - - ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-nav-regs", - 1, 1, &args); - if (ret < 0) { - dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); + dev_err(&pdev->dev, "failed to parse spare-regs\n"); return -EINVAL; } @@ -1548,7 +1484,7 @@ static int q6v5_init_reset(struct q6v5 *qproc) return PTR_ERR(qproc->mss_restart); } - if (qproc->has_alt_reset || qproc->has_halt_nav) { + if (qproc->has_alt_reset || qproc->has_spare_reg) { qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, "pdc_reset"); if (IS_ERR(qproc->pdc_reset)) { @@ -1674,7 +1610,7 @@ static int q6v5_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qproc); - qproc->has_halt_nav = desc->has_halt_nav; + qproc->has_spare_reg = desc->has_spare_reg; ret = q6v5_init_mem(qproc, pdev); if (ret) goto free_rproc; @@ -1816,8 +1752,6 @@ static const struct rproc_hexagon_res sc7180_mss = { .active_clk_names = (char*[]){ "mnoc_axi", "nav", - "mss_nav", - "mss_crypto", NULL }, .active_pd_names = (char*[]){ @@ -1832,7 +1766,7 @@ static const struct rproc_hexagon_res sc7180_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = true, + .has_spare_reg = true, .version = MSS_SC7180, }; @@ -1867,7 +1801,7 @@ static const struct rproc_hexagon_res sdm845_mss = { }, .need_mem_protection = true, .has_alt_reset = true, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_SDM845, }; @@ -1894,7 +1828,7 @@ static const struct rproc_hexagon_res msm8998_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8998, }; @@ -1924,7 +1858,7 @@ static const struct rproc_hexagon_res msm8996_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8996, }; @@ -1957,7 +1891,7 @@ static const struct rproc_hexagon_res msm8916_mss = { }, .need_mem_protection = false, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8916, }; @@ -1998,7 +1932,7 @@ static const struct rproc_hexagon_res msm8974_mss = { }, .need_mem_protection = false, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8974, }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space 2020-04-15 14:51 ` [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space Sibi Sankar @ 2020-04-15 14:51 ` Sibi Sankar 0 siblings, 0 replies; 7+ messages in thread From: Sibi Sankar @ 2020-04-15 14:51 UTC (permalink / raw) To: bjorn.andersson, robh+dt Cc: agross, linux-arm-msm, linux-remoteproc, linux-kernel, evgreen, ohad, Sibi Sankar 7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. So drop all accesses to the MPSS PERPH register space. Issuing HALT NAV request and turning on the mss clocks as part of SSR will no longer be required since the modem firmware will have the necessary fixes to ensure that there are no pending NAV DMA transactions. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_mss.c | 102 +++++------------------------ 1 file changed, 18 insertions(+), 84 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 6a19e0e77236e..3a7352776a319 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -69,13 +69,9 @@ #define AXI_HALTREQ_REG 0x0 #define AXI_HALTACK_REG 0x4 #define AXI_IDLE_REG 0x8 -#define NAV_AXI_HALTREQ_BIT BIT(0) -#define NAV_AXI_HALTACK_BIT BIT(1) -#define NAV_AXI_IDLE_BIT BIT(2) #define AXI_GATING_VALID_OVERRIDE BIT(0) #define HALT_ACK_TIMEOUT_US 100000 -#define NAV_HALT_ACK_TIMEOUT_US 200 /* QDSP6SS_RESET */ #define Q6SS_STOP_CORE BIT(0) @@ -143,7 +139,7 @@ struct rproc_hexagon_res { int version; bool need_mem_protection; bool has_alt_reset; - bool has_halt_nav; + bool has_spare_reg; }; struct q6v5 { @@ -154,13 +150,11 @@ struct q6v5 { void __iomem *rmb_base; struct regmap *halt_map; - struct regmap *halt_nav_map; struct regmap *conn_map; u32 halt_q6; u32 halt_modem; u32 halt_nc; - u32 halt_nav; u32 conn_box; struct reset_control *mss_restart; @@ -205,7 +199,7 @@ struct q6v5 { struct qcom_sysmon *sysmon; bool need_mem_protection; bool has_alt_reset; - bool has_halt_nav; + bool has_spare_reg; int mpss_perm; int mba_perm; const char *hexagon_mdt_image; @@ -426,21 +420,19 @@ static int q6v5_reset_assert(struct q6v5 *qproc) reset_control_assert(qproc->pdc_reset); ret = reset_control_reset(qproc->mss_restart); reset_control_deassert(qproc->pdc_reset); - } else if (qproc->has_halt_nav) { + } else if (qproc->has_spare_reg) { /* * When the AXI pipeline is being reset with the Q6 modem partly * operational there is possibility of AXI valid signal to * glitch, leading to spurious transactions and Q6 hangs. A work * around is employed by asserting the AXI_GATING_VALID_OVERRIDE - * BIT before triggering Q6 MSS reset. Both the HALTREQ and - * AXI_GATING_VALID_OVERRIDE are withdrawn post MSS assert - * followed by a MSS deassert, while holding the PDC reset. + * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE + * is withdrawn post MSS assert followed by a MSS deassert, + * while holding the PDC reset. */ reset_control_assert(qproc->pdc_reset); regmap_update_bits(qproc->conn_map, qproc->conn_box, AXI_GATING_VALID_OVERRIDE, 1); - regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav, - NAV_AXI_HALTREQ_BIT, 0); reset_control_assert(qproc->mss_restart); reset_control_deassert(qproc->pdc_reset); regmap_update_bits(qproc->conn_map, qproc->conn_box, @@ -463,7 +455,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc) ret = reset_control_reset(qproc->mss_restart); writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); reset_control_deassert(qproc->pdc_reset); - } else if (qproc->has_halt_nav) { + } else if (qproc->has_spare_reg) { ret = reset_control_reset(qproc->mss_restart); } else { ret = reset_control_deassert(qproc->mss_restart); @@ -760,32 +752,6 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc, regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); } -static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc, - struct regmap *halt_map, - u32 offset) -{ - unsigned int val; - int ret; - - /* Check if we're already idle */ - ret = regmap_read(halt_map, offset, &val); - if (!ret && (val & NAV_AXI_IDLE_BIT)) - return; - - /* Assert halt request */ - regmap_update_bits(halt_map, offset, NAV_AXI_HALTREQ_BIT, - NAV_AXI_HALTREQ_BIT); - - /* Wait for halt ack*/ - regmap_read_poll_timeout(halt_map, offset, val, - (val & NAV_AXI_HALTACK_BIT), - 5, NAV_HALT_ACK_TIMEOUT_US); - - ret = regmap_read(halt_map, offset, &val); - if (ret || !(val & NAV_AXI_IDLE_BIT)) - dev_err(qproc->dev, "port failed halt\n"); -} - static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) { unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; @@ -950,9 +916,6 @@ static int q6v5_mba_load(struct q6v5 *qproc) halt_axi_ports: q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); - if (qproc->has_halt_nav) - q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, - qproc->halt_nav); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); reclaim_mba: @@ -1000,9 +963,6 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); - if (qproc->has_halt_nav) - q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, - qproc->halt_nav); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); if (qproc->version == MSS_MSM8996) { /* @@ -1433,36 +1393,12 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) qproc->halt_modem = args.args[1]; qproc->halt_nc = args.args[2]; - if (qproc->has_halt_nav) { - struct platform_device *nav_pdev; - + if (qproc->has_spare_reg) { ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-nav-regs", + "qcom,spare-regs", 1, 0, &args); if (ret < 0) { - dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); - return -EINVAL; - } - - nav_pdev = of_find_device_by_node(args.np); - of_node_put(args.np); - if (!nav_pdev) { - dev_err(&pdev->dev, "failed to get mss clock device\n"); - return -EPROBE_DEFER; - } - - qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, NULL); - if (!qproc->halt_nav_map) { - dev_err(&pdev->dev, "failed to get map from device\n"); - return -EINVAL; - } - qproc->halt_nav = args.args[0]; - - ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-nav-regs", - 1, 1, &args); - if (ret < 0) { - dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); + dev_err(&pdev->dev, "failed to parse spare-regs\n"); return -EINVAL; } @@ -1548,7 +1484,7 @@ static int q6v5_init_reset(struct q6v5 *qproc) return PTR_ERR(qproc->mss_restart); } - if (qproc->has_alt_reset || qproc->has_halt_nav) { + if (qproc->has_alt_reset || qproc->has_spare_reg) { qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, "pdc_reset"); if (IS_ERR(qproc->pdc_reset)) { @@ -1674,7 +1610,7 @@ static int q6v5_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qproc); - qproc->has_halt_nav = desc->has_halt_nav; + qproc->has_spare_reg = desc->has_spare_reg; ret = q6v5_init_mem(qproc, pdev); if (ret) goto free_rproc; @@ -1816,8 +1752,6 @@ static const struct rproc_hexagon_res sc7180_mss = { .active_clk_names = (char*[]){ "mnoc_axi", "nav", - "mss_nav", - "mss_crypto", NULL }, .active_pd_names = (char*[]){ @@ -1832,7 +1766,7 @@ static const struct rproc_hexagon_res sc7180_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = true, + .has_spare_reg = true, .version = MSS_SC7180, }; @@ -1867,7 +1801,7 @@ static const struct rproc_hexagon_res sdm845_mss = { }, .need_mem_protection = true, .has_alt_reset = true, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_SDM845, }; @@ -1894,7 +1828,7 @@ static const struct rproc_hexagon_res msm8998_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8998, }; @@ -1924,7 +1858,7 @@ static const struct rproc_hexagon_res msm8996_mss = { }, .need_mem_protection = true, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8996, }; @@ -1957,7 +1891,7 @@ static const struct rproc_hexagon_res msm8916_mss = { }, .need_mem_protection = false, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8916, }; @@ -1998,7 +1932,7 @@ static const struct rproc_hexagon_res msm8974_mss = { }, .need_mem_protection = false, .has_alt_reset = false, - .has_halt_nav = false, + .has_spare_reg = false, .version = MSS_MSM8974, }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/2] Drop all accesses to MPSS PERPH register space 2020-04-15 14:51 [PATCH 0/2] Drop all accesses to MPSS PERPH register space Sibi Sankar 2020-04-15 14:51 ` [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs Sibi Sankar 2020-04-15 14:51 ` [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space Sibi Sankar @ 2020-04-29 17:27 ` Evan Green 2020-05-13 6:20 ` patchwork-bot+linux-remoteproc 3 siblings, 0 replies; 7+ messages in thread From: Evan Green @ 2020-04-29 17:27 UTC (permalink / raw) To: Sibi Sankar Cc: Bjorn Andersson, Rob Herring, Andy Gross, linux-arm-msm, linux-remoteproc, LKML, Ohad Ben Cohen On Wed, Apr 15, 2020 at 7:51 AM Sibi Sankar <sibis@codeaurora.org> wrote: > > 7C retail devices using MSA based boot will result in a fuse combination > which will prevent accesses to MSS PERPH register space where the mpss > clocks and halt-nav reside. Hence requesting a halt-nav as part of the > SSR sequence will result in a NoC error. Issuing HALT NAV request and > turning on the mss clocks as part of SSR will no longer be required > since the modem firmware will have the necessary fixes to ensure that > there are no pending NAV DMA transactions thereby ensuring a smooth > SSR. > > Sibi Sankar (2): > dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs > remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space I haven't tested things in the "production" fuse configuration yet, but in my current configuration I've got a tree that's running the modem well. Tested-by: Evan Green <evgreen@chromium.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/2] Drop all accesses to MPSS PERPH register space 2020-04-15 14:51 [PATCH 0/2] Drop all accesses to MPSS PERPH register space Sibi Sankar ` (2 preceding siblings ...) 2020-04-29 17:27 ` [PATCH 0/2] Drop all " Evan Green @ 2020-05-13 6:20 ` patchwork-bot+linux-remoteproc 3 siblings, 0 replies; 7+ messages in thread From: patchwork-bot+linux-remoteproc @ 2020-05-13 6:20 UTC (permalink / raw) To: Sibi Sankar; +Cc: linux-remoteproc Hello: This series was applied to andersson/remoteproc.git (refs/heads/for-next). On Wed, 15 Apr 2020 20:21:08 +0530 you wrote: > 7C retail devices using MSA based boot will result in a fuse combination > which will prevent accesses to MSS PERPH register space where the mpss > clocks and halt-nav reside. Hence requesting a halt-nav as part of the > SSR sequence will result in a NoC error. Issuing HALT NAV request and > turning on the mss clocks as part of SSR will no longer be required > since the modem firmware will have the necessary fixes to ensure that > there are no pending NAV DMA transactions thereby ensuring a smooth > SSR. > > [...] Here is a summary with links: - [1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs https://git.kernel.org/andersson/remoteproc/c/e62e3acd61d36b07878cd33a868a5797fe1e25b5 - [2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space https://git.kernel.org/andersson/remoteproc/c/a9fdc79d488623d36341f0f3d08f5aa1bedb9d53 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.wiki.kernel.org/userdoc/pwbot ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-13 6:20 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-04-15 14:51 [PATCH 0/2] Drop all accesses to MPSS PERPH register space Sibi Sankar 2020-04-15 14:51 ` [PATCH 1/2] dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs Sibi Sankar 2020-04-15 14:51 ` Sibi Sankar 2020-04-15 14:51 ` [PATCH 2/2] remoteproc: qcom_q6v5_mss: Drop accesses to MPSS PERPH register space Sibi Sankar 2020-04-15 14:51 ` Sibi Sankar 2020-04-29 17:27 ` [PATCH 0/2] Drop all " Evan Green 2020-05-13 6:20 ` patchwork-bot+linux-remoteproc
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