Re: [PATCH v2 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon

[Stephan Gerhold <stephan@gerhold.net>]

Hi Bjorn,

On Mon, Jun 22, 2020 at 12:59:55AM -0700, Bjorn Andersson wrote:
> In modern Qualcomm platforms the mutex region of the TCSR is forked off
> into its own block, all with a offset of 0 and stride of 4096, and in
> some of these platforms no other registers in this region is accessed
> from Linux.
> 
> So add support for directly memory mapping this register space, to avoid
> the need to represent this block using a syscon.
> 
> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> 
> Changes since v1:
> - Use devm_platform_ioremap_resource()
> 
>  drivers/hwspinlock/qcom_hwspinlock.c | 70 +++++++++++++++++++++-------
>  1 file changed, 54 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
> index f0da544b14d2..364710966665 100644
> --- a/drivers/hwspinlock/qcom_hwspinlock.c
> +++ b/drivers/hwspinlock/qcom_hwspinlock.c
> @@ -70,41 +70,79 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
>  
> -static int qcom_hwspinlock_probe(struct platform_device *pdev)
> +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
> +						   u32 *base, u32 *stride)
>  {
> -	struct hwspinlock_device *bank;
>  	struct device_node *syscon;
> -	struct reg_field field;
>  	struct regmap *regmap;
> -	size_t array_size;
> -	u32 stride;
> -	u32 base;
>  	int ret;
> -	int i;
>  
>  	syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
> -	if (!syscon) {
> -		dev_err(&pdev->dev, "no syscon property\n");
> -		return -ENODEV;
> -	}
> +	if (!syscon)
> +		return ERR_PTR(-ENODEV);
>  
>  	regmap = syscon_node_to_regmap(syscon);
>  	of_node_put(syscon);
>  	if (IS_ERR(regmap))
> -		return PTR_ERR(regmap);
> +		return regmap;
>  
> -	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base);
> +	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
>  	if (ret < 0) {
>  		dev_err(&pdev->dev, "no offset in syscon\n");
> -		return -EINVAL;
> +		return ERR_PTR(-EINVAL);
>  	}
>  
> -	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride);
> +	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
>  	if (ret < 0) {
>  		dev_err(&pdev->dev, "no stride syscon\n");
> -		return -EINVAL;
> +		return ERR_PTR(-EINVAL);
>  	}
>  
> +	return regmap;
> +}
> +
> +static const struct regmap_config tcsr_mutex_config = {
> +	.reg_bits		= 32,
> +	.reg_stride		= 4,
> +	.val_bits		= 32,
> +	.max_register		= 0x40000,

Where does the 0x40000 come from?

It seems like this driver has QCOM_MUTEX_NUM_LOCKS = 32 hardcoded.
With a stride of 4096 = 0x1000 you get 0x1000 * 32 = 0x20000.

This is also the reg size used in msm8996.dtsi and msm8916.dtsi for
example, while sdm845.dtsi and sm8250.dtsi specify 0x40000.
Are you not exposing all available locks on the newer SoCs?

I'm not sure how important max_register is... But I guess it should be
either correct for all SoCs or not specified at all (since it's
optional)?

(That is assuming the hwlock can be also used directly via MMIO on
 MSM8996 and MSM8916. It looks to me like it has its own register
 space there as well...)

Thanks,
Stephan