From: "Arnd Bergmann" <arnd@arndb.de>
To: "Conor.Dooley" <conor.dooley@microchip.com>,
Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Geert Uytterhoeven" <geert+renesas@glider.be>,
"Heiko Stübner" <heiko@sntech.de>, guoren <guoren@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Samuel Holland" <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Fri, 31 Mar 2023 13:36:11 +0200 [thread overview]
Message-ID: <08eace10-3eee-481a-b1b4-de58e94cd828@app.fastmail.com> (raw)
In-Reply-To: <50e932df-cb20-4679-b911-fd9d7f0f2c1d@spud>
On Fri, Mar 31, 2023, at 12:55, Conor Dooley wrote:
> On Fri, Mar 31, 2023 at 11:37:30AM +0100, Lad, Prabhakar wrote:
>>
>
> Does that actually work? I don't think it does.
> If you try to enable RISCV_ISA_ZICBOM then you won't get
> RISC_DMA_NONCOHERENT turned on. Run menuconfig and disable support for
> Renesas, SiFive and T-Head SoCs & you can replicate.
Right, the circular dependency has to be broken in some form.
> I think one of RISCV_ISA_ZICBOM and RISCV_DMA_NONCOHERENT should just be
> dropped, although I don't know which one to pick!
> Making RISCV_DMA_NONCOHERENT user selectable probably makes the most
> sense.
That sounds good to me.
Arnd
next prev parent reply other threads:[~2023-03-31 11:36 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 20:42 [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Prabhakar
2023-03-30 20:42 ` [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-03-30 21:34 ` Arnd Bergmann
2023-03-31 7:54 ` Conor Dooley
2023-03-31 7:58 ` Arnd Bergmann
2023-03-31 10:37 ` Lad, Prabhakar
2023-03-31 10:44 ` Arnd Bergmann
2023-03-31 12:11 ` Lad, Prabhakar
2023-04-03 17:00 ` Lad, Prabhakar
2023-03-31 10:55 ` Conor Dooley
2023-03-31 11:36 ` Arnd Bergmann [this message]
2023-03-31 7:31 ` Geert Uytterhoeven
2023-03-31 10:45 ` Lad, Prabhakar
2023-03-31 12:24 ` Conor Dooley
2023-04-03 18:23 ` Lad, Prabhakar
2023-04-03 18:31 ` Conor Dooley
2023-04-04 5:29 ` Christoph Hellwig
2023-04-04 6:24 ` Biju Das
2023-04-04 15:42 ` Christoph Hellwig
2023-04-05 6:08 ` Biju Das
2023-04-07 0:03 ` Andrea Parri
2023-04-07 5:33 ` Christoph Hellwig
2023-04-04 6:50 ` Arnd Bergmann
2023-04-04 6:59 ` Conor Dooley
2023-04-06 18:59 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-03-30 20:42 ` [PATCH v7 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-03-30 20:42 ` [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-03-31 10:21 ` Conor Dooley
2023-03-31 10:47 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-03-31 12:45 ` Conor Dooley
2023-03-31 20:17 ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-03-31 7:37 ` Geert Uytterhoeven
2023-03-31 7:37 ` Geert Uytterhoeven
2023-03-31 18:05 ` [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Conor Dooley
2023-03-31 20:09 ` Lad, Prabhakar
2023-03-31 20:15 ` Conor Dooley
2023-04-01 1:47 ` Icenowy Zheng
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